From f8712482eeec5fa3274d47eb7ce21044f59785e3 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 21 May 2025 10:48:22 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E8=AE=BF=E9=97=AE=E5=AF=84?= =?UTF-8?q?=E5=AD=98=E5=99=A8=E7=A9=BA=E9=97=B4=E8=8C=83=E5=9B=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index dfe78a5..f1a3388 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -424,15 +424,15 @@ trait InterfaceMCUop{ this: InterfaceBase => )) datar := MuxCase( 0.U, Array( - ((addrr & "hFF00".U) === "h0000".U) -> AcquireReg(addr = addrr), - ((addrr & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar, - ((addrr & "hFF00".U) === "h1000".U) -> 0.U, - ((addrr & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar, - ((addrr & "hFF00".U) === "h2000".U) -> 0.U, - ((addrr & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar, - ((addrr & "hFF00".U) === "h3000".U) -> 0.U, - ((addrr & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar, - ((addrr & "hFF00".U) === "h4000".U) -> 0.U, + ((addrr & "hF800".U) === "h0000".U) -> AcquireReg(addr = addrr), + ((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar, + ((addrr & "hF800".U) === "h1000".U) -> 0.U, + ((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar, + ((addrr & "hF800".U) === "h2000".U) -> 0.U, + ((addrr & "hF800".U) === "h2800".U) -> io.sram_r(2).datar, + ((addrr & "hF800".U) === "h3000".U) -> 0.U, + ((addrr & "hF800".U) === "h3800".U) -> io.sram_r(3).datar, + ((addrr & "hF800".U) === "h4000".U) -> 0.U, )) iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)