diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index dfe78a5..f1a3388 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -424,15 +424,15 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   ))
 
   datar := MuxCase( 0.U, Array(
-      ((addrr & "hFF00".U) === "h0000".U) -> AcquireReg(addr = addrr),
-      ((addrr & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
-      ((addrr & "hFF00".U) === "h1000".U) -> 0.U,
-      ((addrr & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
-      ((addrr & "hFF00".U) === "h2000".U) -> 0.U,
-      ((addrr & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar,
-      ((addrr & "hFF00".U) === "h3000".U) -> 0.U,
-      ((addrr & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar,
-      ((addrr & "hFF00".U) === "h4000".U) -> 0.U,
+      ((addrr & "hF800".U) === "h0000".U) -> AcquireReg(addr = addrr),
+      ((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
+      ((addrr & "hF800".U) === "h1000".U) -> 0.U,
+      ((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
+      ((addrr & "hF800".U) === "h2000".U) -> 0.U,
+      ((addrr & "hF800".U) === "h2800".U) -> io.sram_r(2).datar,
+      ((addrr & "hF800".U) === "h3000".U) -> 0.U,
+      ((addrr & "hF800".U) === "h3800".U) -> io.sram_r(3).datar,
+      ((addrr & "hF800".U) === "h4000".U) -> 0.U,
     ))
 
   iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)