From f700b11e84c1fa690a894a1321b8bebd5f834700 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Wed, 10 Sep 2025 09:12:52 +0800
Subject: [PATCH] =?UTF-8?q?latch=E4=BD=BF=E7=94=A8=E4=B8=BB=E7=AB=99offset?=
 =?UTF-8?q?=E6=A0=A1=E5=87=86=E5=90=8E=E6=97=B6=E9=97=B4?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 6064304..d0a8faf 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -1254,7 +1254,7 @@ trait InterfaceEvent{ this: InterfaceBase =>
         isPosedgeLatch(i) := true.B
       }
       when(~isPosedgeLatch(i)){
-        posedgeTimeStampLatch(i) := cReg.timeStamp
+        posedgeTimeStampLatch(i) := cReg.recoTimeStamp
       }
     }
 
@@ -1266,24 +1266,24 @@ trait InterfaceEvent{ this: InterfaceBase =>
         isNegedgeLatch(i) := true.B
       }
       when(~isNegedgeLatch(i)){
-        negedgeTimeStampLatch(i) := cReg.timeStamp
+        negedgeTimeStampLatch(i) := cReg.recoTimeStamp
       }
     }
 
     when( io.uSMenq.reduce(_|_) ){
-      mcuSMTimeStampEnq := cReg.timeStamp
+      mcuSMTimeStampEnq := cReg.recoTimeStamp
     }
 
     when( io.dSMdeq.reduce(_|_) ){
-      mcuSMTimeStampDeq := cReg.timeStamp
+      mcuSMTimeStampDeq := cReg.recoTimeStamp
     }
 
     when( io.lvdsSMEnq.reduce(_|_) ){
-      lvdsSMTimeStampEnq := cReg.timeStamp
+      lvdsSMTimeStampEnq := cReg.recoTimeStamp
     }
 
     when( io.lvdsSMDeq.reduce(_|_) ){
-      lvdsSMTimeStampDeq := cReg.timeStamp
+      lvdsSMTimeStampDeq := cReg.recoTimeStamp
     }
 
     cReg.event.latchCtl(i) := (isPosedgeOnce(i) << 2) | (isNegedgeOnce(i) << 3)