diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 6064304..d0a8faf 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -1254,7 +1254,7 @@ trait InterfaceEvent{ this: InterfaceBase =>
         isPosedgeLatch(i) := true.B
       }
       when(~isPosedgeLatch(i)){
-        posedgeTimeStampLatch(i) := cReg.timeStamp
+        posedgeTimeStampLatch(i) := cReg.recoTimeStamp
       }
     }
 
@@ -1266,24 +1266,24 @@ trait InterfaceEvent{ this: InterfaceBase =>
         isNegedgeLatch(i) := true.B
       }
       when(~isNegedgeLatch(i)){
-        negedgeTimeStampLatch(i) := cReg.timeStamp
+        negedgeTimeStampLatch(i) := cReg.recoTimeStamp
       }
     }
 
     when( io.uSMenq.reduce(_|_) ){
-      mcuSMTimeStampEnq := cReg.timeStamp
+      mcuSMTimeStampEnq := cReg.recoTimeStamp
     }
 
     when( io.dSMdeq.reduce(_|_) ){
-      mcuSMTimeStampDeq := cReg.timeStamp
+      mcuSMTimeStampDeq := cReg.recoTimeStamp
     }
 
     when( io.lvdsSMEnq.reduce(_|_) ){
-      lvdsSMTimeStampEnq := cReg.timeStamp
+      lvdsSMTimeStampEnq := cReg.recoTimeStamp
     }
 
     when( io.lvdsSMDeq.reduce(_|_) ){
-      lvdsSMTimeStampDeq := cReg.timeStamp
+      lvdsSMTimeStampDeq := cReg.recoTimeStamp
     }
 
     cReg.event.latchCtl(i) := (isPosedgeOnce(i) << 2) | (isNegedgeOnce(i) << 3)