From f609945a6adca842703d098eccc732f912a199c6 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 5 Sep 2025 09:35:29 +0800 Subject: [PATCH] =?UTF-8?q?8b10b=E7=BC=96=E7=A0=81=E5=AE=8C=E6=88=90?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/b8b10.scala | 88 ++++++++++++++++++++++- 1 file changed, 85 insertions(+), 3 deletions(-) diff --git a/src/main/scala/backBoard/ebus/b8b10.scala b/src/main/scala/backBoard/ebus/b8b10.scala index af8927a..e925411 100644 --- a/src/main/scala/backBoard/ebus/b8b10.scala +++ b/src/main/scala/backBoard/ebus/b8b10.scala @@ -12,9 +12,7 @@ class b8b10Encode extends Module with RequireAsyncReset{ }) val rd = RegInit(false.B) - - val rdCalNext = Wire(SInt(8.W)) - val rdCal = RegNext(rdCalNext, 0.S(8.W)) + val b5b6LookUp = Mux1H(Seq( (io.dataIn(4,0) === "b00000".U) -> Mux( rd, "b100111".U(6.W), "b011000".U(6.W) ), @@ -51,6 +49,90 @@ class b8b10Encode extends Module with RequireAsyncReset{ (io.dataIn(4,0) === "b11111".U) -> Mux( rd, "b101011".U(6.W), "b010100".U(6.W) ) )) + val b3b4LookUp = Mux1H(Seq( + (io.dataIn(7,5) === "b000".U) -> Mux( b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ), + (io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W), + (io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W), + (io.dataIn(7,5) === "b011".U) -> Mux( b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ), + (io.dataIn(7,5) === "b100".U) -> Mux( b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ), + (io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W), + (io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W), + (io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), + ((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W), // 17, 18, 20 are special cases + ((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) & b5b6RD) -> "b1000".U(4.W), // 11, 13, 14 are special cases + ) + )) + + val b5b6RD = Mux1H(Seq( + (io.dataIn(4,0) === "b00000".U) -> ~rd, + (io.dataIn(4,0) === "b00001".U) -> ~rd, + (io.dataIn(4,0) === "b00010".U) -> ~rd, + (io.dataIn(4,0) === "b00011".U) -> rd, + (io.dataIn(4,0) === "b00100".U) -> ~rd, + (io.dataIn(4,0) === "b00101".U) -> rd, + (io.dataIn(4,0) === "b00110".U) -> rd, + (io.dataIn(4,0) === "b00111".U) -> rd + (io.dataIn(4,0) === "b01000".U) -> ~rd, + (io.dataIn(4,0) === "b01001".U) -> rd, + (io.dataIn(4,0) === "b01010".U) -> rd, + (io.dataIn(4,0) === "b01011".U) -> rd, + (io.dataIn(4,0) === "b01100".U) -> rd, + (io.dataIn(4,0) === "b01101".U) -> rd, + (io.dataIn(4,0) === "b01110".U) -> rd, + (io.dataIn(4,0) === "b01111".U) -> ~rd, + (io.dataIn(4,0) === "b10000".U) -> ~rd, + (io.dataIn(4,0) === "b10001".U) -> rd, + (io.dataIn(4,0) === "b10010".U) -> rd, + (io.dataIn(4,0) === "b10011".U) -> rd, + (io.dataIn(4,0) === "b10100".U) -> rd, + (io.dataIn(4,0) === "b10101".U) -> rd, + (io.dataIn(4,0) === "b10110".U) -> rd, + (io.dataIn(4,0) === "b10111".U) -> ~rd, + (io.dataIn(4,0) === "b11000".U) -> ~rd, + (io.dataIn(4,0) === "b11001".U) -> rd, + (io.dataIn(4,0) === "b11010".U) -> rd, + (io.dataIn(4,0) === "b11011".U) -> ~rd, + (io.dataIn(4,0) === "b11100".U) -> rd, + (io.dataIn(4,0) === "b11101".U) -> ~rd, + (io.dataIn(4,0) === "b11110".U) -> ~rd, + (io.dataIn(4,0) === "b11111".U) -> ~rd, + )) + + val b3b4RD = Mux1H(Seq( + (io.dataIn(7,5) === "b000".U) -> ~b5b6RD, + (io.dataIn(7,5) === "b001".U) -> b5b6RD, + (io.dataIn(7,5) === "b010".U) -> b5b6RD, + (io.dataIn(7,5) === "b011".U) -> b5b6RD, + (io.dataIn(7,5) === "b100".U) -> ~b5b6RD, + (io.dataIn(7,5) === "b101".U) -> b5b6RD, + (io.dataIn(7,5) === "b110".U) -> b5b6RD, + (io.dataIn(7,5) === "b111".U) -> ~b5b6RD, + )) + + io.dataOut := Cat(b5b6LookUp, b3b4LookUp) + + when (io.isEnable) { + rd := b3b4RD + assert( io.dataOut(4,0) =/= 0.U && io.dataOut(4,0) =/= 31.U, "Invalid 8b10b encoding Output!") + assert( io.dataOut(5,1) =/= 0.U && io.dataOut(5,1) =/= 31.U, "Invalid 8b10b encoding Output!") + assert( io.dataOut(6,2) =/= 0.U && io.dataOut(6,2) =/= 31.U, "Invalid 8b10b encoding Output!") + assert( io.dataOut(7,3) =/= 0.U && io.dataOut(7,3) =/= 31.U, "Invalid 8b10b encoding Output!") + assert( io.dataOut(8,4) =/= 0.U && io.dataOut(8,4) =/= 31.U, "Invalid 8b10b encoding Output!") + assert( io.dataOut(9,5) =/= 0.U && io.dataOut(9,5) =/= 31.U, "Invalid 8b10b encoding Output!") + + } } + +class b8b10Decode extends Module with RequireAsyncReset{ + val io = IO(new Bundle{ + val dataIn = Input(UInt(10.W)) + val isEnable = Input(Bool()) + val dataOut = Output(UInt(8.W)) + }) + + + + +}