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This commit is contained in:
Ruige Lee
2023-08-18 12:10:47 +00:00
parent 6fa2ef5f6e
commit f3a44f0b31
5 changed files with 339 additions and 110 deletions
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195
src/main/scala/backBoard/BackBoardMst.scala
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@@ -29,55 +29,67 @@ class BackBoardMstIO extends Bundle{
} }
class BackBoardMstBase extends Module{ class BackBoardMstBase extends RawModule{
val io: BackBoardMstIO = IO(new BackBoardMstIO) val io: BackBoardMstIO = IO(new BackBoardMstIO)
val fsmcSlv = Module(new FSMCSlv)
fsmcSlv.io.FSMC <> io.FSMC
val lvdsMst = Module(new Lvds_Bus_Master) val lvdsMst = Module(new Lvds_Bus_Master)
val mirrorDown = Module(new MirrorSRAM)
val mirrorUp = Module(new MirrorSRAM)
val status = Reg(UInt(8.W))
val slvNum = Reg(UInt(5.W))
mirrorDown.io.clock := io.ides_pclk.asBool
val ( cnt, trigger ) = Counter(Range( 0,1023)) mirrorDown.io.reset := io.reset.asBool
mirrorUp.io.clock := io.ides_pclk.asBool
mirrorUp.io.reset := io.reset.asBool
val status = RegInit(0.U(8.W))
val slvNum = RegInit(0.U(6.W))
val mirror = Module(new MirrorSRAM)
mirror.io.clock := io.ides_pclk.asBool
mirror.io.reset := io.reset.asBool
} }
trait BackBoardMstFSMC{ this: BackBoardMstBase => trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B ) withClockAndReset( io.ides_pclk.asClock, io.reset ){
val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B ) val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B ) val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B ) val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B )
val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B ) val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B )
val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B )
io.FSMC.dataOEn := io.FSMC.oen io.FSMC.dataOEn := io.FSMC.oen
mirrorDown.io.we := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
mirrorDown.io.addrw := fsmcAddrSync(10,0)
mirrorDown.io.dataw := fsmcdataInSync
// mirrorUp.io.ce := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
mirrorUp.io.addrr := fsmcAddrSync(10,0)
val regOut = Wire(UInt(8.W))
io.FSMC.dataOut := mirror.io.datar_a io.FSMC.dataOut := Mux( fsmcAddrSync.extract(12), regOut, mirrorUp.io.datar)
mirror.io.ce_a := (~fsmcCEnSync & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync | ~fsmcWEnSync) )
mirror.io.we_a := ~fsmcWEnSync regOut := Mux1H(Seq(
mirror.io.addr_a := fsmcAddrSync(10,0) (fsmcAddrSync(10,0) === 0.U) -> status,
mirror.io.dataw_a := fsmcdataInSync (fsmcAddrSync(10,0) === 1.U) -> slvNum,
))
when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 0.U) ){
status := fsmcdataInSync
}
when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 1.U) ){
slvNum := fsmcdataInSync
}
}
} }
@@ -94,29 +106,114 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
lvdsMst.io.tx_start := false.B lvdsMst.io.tx_start := false.B
.elsewhen( cnt === 0.U ){
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val stateCur = RegInit(0.U(3.W))
val ( cnt, trigger ) = Counter(Range( 0,1023))
val addrr = RegInit(0.U)
val addrw = RegInit(0.U)
when( trigger ){
stateCur := 0.U
addrr := 0.U
addrw := 0.U
lvdsMst.io.frame_info_update_en := true.B
lvdsMst.io.slave_type_num := Cat( "b000".U(3.W), slvNum )
lvdsMst.io.slave_data_length := (8/8*4*8-1).U
lvdsMst.io.tx_start := false.B
} .elsewhen( stateCur === 0.U ){
stateCur := 1.U
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := true.B
} .elsewhen( stateCur === 1.U ){
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
stateCur := 2.U
}
} .elsewhen( stateCur === 2.U ){
stateCur := 3.U
lvdsMst.io.frame_info_update_en := true.B
lvdsMst.io.slave_type_num := Cat( "b10".U(2.W), 0.U(6.W) )
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
addrr := 0.U
addrw := 0.U
} .elsewhen( stateCur === 3.U ){
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := true.B
} .elsewhen( stateCur === 4.U ){
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
when( lvdsMst.io.tx_data_ready ){
addrr := addrr + 1.U
}
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
stateCur := 5.U
}
} .elsewhen( stateCur === 5.U ){
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
} .otherwise{
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
assert(false.B)
}
when( lvdsMst.io.rx_data_valid ){
assert( (stateCur === 4.U) || (stateCur === 5.U) )
addrw := addrw + 1.U
}
lvdsMst.io.tx_data_in := mirrorDown.io.datar
mirrorDown.io.addrr := addrr
} .elsewhen( cnt === 1.U ){ mirrorUp.io.we := lvdsMst.io.rx_data_valid
lvdsMst.io.tx_start := true.B mirrorUp.io.dataw := lvdsMst.io.rx_data_out
mirrorUp.io.addrw := addrw
} }
lvdsMst.io.frame_info_update_en := (cnt === 0.U)
lvdsMst.io.slave_type_num := Cat( "b00".U(2.W), slvNum )
lvdsMst.io.slave_data_length := (8/8*4*8-1).U
lvdsMst.io.tx_start = Input(Bool())
lvdsMst.io.tx_data_in = Input(UInt(8.W))
lvdsMst.io.tx_data_ready = Output(Bool())
lvdsMst.io.downstream_busy = Output(Bool())
lvdsMst.io.rx_data_out = Output(UInt(8.W))
lvdsMst.io.rx_data_valid = Output(Bool())
lvdsMst.io.upstream_crc_valid = Output(Bool())
lvdsMst.io.upstream_crc_err = Output(Bool())
lvdsMst.io.upstream_crc_err_count = Output(UInt(8.W))
lvdsMst.io.upstream_cdr_err = Output(Bool())
} }

139
src/main/scala/backBoard/BackBoardSlv.scala Normal file
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@@ -0,0 +1,139 @@
package BACK
import chisel3._
import chisel3.util._
class BackBoardSlvIO extends Bundle{
val reset = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val lvds_down_din = Input(Bool())
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
val lvds_up_dout = Output(Bool())
}
abstract class BackBoardSlvBase extends RawModule{
val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
val lvdsSlv = Module(new Lvds_Bus_Slave)
lvdsSlv.io.rst_n := ~io.reset
lvdsSlv.io.oser_pclk := io.oser_pclk
lvdsSlv.io.oser_fclk := io.oser_fclk
lvdsSlv.io.ides_pclk := io.ides_pclk
lvdsSlv.io.ides_fclk := io.ides_fclk
lvdsSlv.io.lvds_down_din := io.lvds_down_din
lvdsSlv.io.lvds_down_dout := io.lvds_down_dout
lvdsSlv.io.lvds_up_din := io.lvds_up_din
lvdsSlv.io.lvds_up_dout := io.lvds_up_dout
val downReg = Reg(Vec(32, UInt(8.W)))
val upReg = Reg(Vec(32, UInt(8.W)))
// val downstream_rx_data_valid = Output(Bool())
// val downstream_rx_data_out = Output(UInt(8.W))
// val downstream_rx_crc_valid = Output(Bool())
// val downstream_rx_crc_err = Output(Bool())
// val downstream_rx_crc_err_counter = Output(UInt(8.W))
// val downstream_rx_cdr_err = Output(Bool())
// val downstream_sync = Output(Bool())
val upstream_tx_data_ready = Output(Bool())
val upstream_tx_data_in = Input(UInt(8.W))
// val upstream_rx_crc_valid = Output(Bool())
// val upstream_rx_crc_err = Output(Bool())
// val upstream_rx_crc_err_counter = Output(UInt(8.W))
// val upstream_rx_cdr_err = Output(Bool())
}
trait BackBoardSlvDown{ this: BackBoardSlvBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val downCnt = RegInit(0.U(6.W))
val downTimeoutEn = RegInit( false.B )
val downTimeoutRst = (downCnt === 0.U & downstream_rx_data_valid)
val ( _, downTimeout ) = Counter( Range( 0,1023 ), downTimeoutEn, downTimeoutRst )
when( io.reset ){
for( i <- 0 until 32 ){
downReg(i) := 0.U
}
} .otherwise{
when( downstream_rx_data_valid ){
downReg(downCnt) := downstream_rx_data_out
}
}
when( downTimeout ){
downTimeoutEn := false.B
} .elsewhen( downCnt === 32.U ){
downTimeoutEn := false.B
} .elsewhen(downCnt === 0.U & downstream_rx_data_valid){
downTimeoutEn := true.B
}
when( downTimeout ){
downCnt := 0.U
}.elsewhen( downCnt === 32.U ){
downCnt := 0.U
}.elsewhen( downstream_rx_data_valid ){
downCnt := downCnt + 1.U
}
}
}
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val upCnt = RegInit(0.U(6.W))
val upTimeoutEn = RegInit( false.B )
val upTimeoutRst = (upCnt === 0.U & upstream_tx_data_ready)
val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
// when( upstream_tx_data_ready ){
// upstream_tx_data_ready := upReg(upCnt)
// }
when( io.reset ){
for( i <- 0 until 32 ){
upReg(i) := 0.U
}
} .otherwise{
}
when( upTimeout ){
upTimeoutEn := false.B
} .elsewhen( upCnt === 32.U ){
upTimeoutEn := false.B
} .elsewhen(upCnt === 0.U & upstream_tx_data_ready){
upTimeoutEn := true.B
}
when( upTimeout ){
upCnt := 0.U
}.elsewhen( upCnt === 32.U ){
upCnt := 0.U
}.elsewhen( upstream_tx_data_ready ){
upCnt := upCnt + 1.U
}
}
}

113
src/main/scala/backBoard/MirrorSRAM.scala
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@@ -6,92 +6,85 @@ import chisel3.util._
class MirrorSRAMIO extends Bundle{ class MirrorSRAMIO extends Bundle{
val datar = Output(UInt(8.W))
val dataw = Input(UInt(8.W))
val clock = Input(Bool())
val reset = Input(Bool())
val we = Input(Bool())
val addrr = Input(UInt(11.W))
val addrw = Input(UInt(11.W))
val datar_a = Output(UInt(8.W))
val datar_b = Output(UInt(8.W))
val clk_a = Input(Bool()) // val datar_a = Output(UInt(8.W))
val clk_b = Input(Bool()) // val datar_b = Output(UInt(8.W))
val reset_a = Input(Bool()) // val clk_a = Input(Bool())
val reset_b = Input(Bool()) // val clk_b = Input(Bool())
val ce_a = Input(Bool()) // val reset_a = Input(Bool())
val ce_b = Input(Bool()) // val reset_b = Input(Bool())
val we_a = Input(Bool()) // val ce_a = Input(Bool())
val we_b = Input(Bool()) // val ce_b = Input(Bool())
val addr_a = Input(UInt(11.W)) // val we_a = Input(Bool())
val addr_b = Input(UInt(11.W)) // val we_b = Input(Bool())
val dataw_a = Input(UInt(8.W)) // val addr_a = Input(UInt(11.W))
val dataw_b = Input(UInt(8.W)) // val addr_b = Input(UInt(11.W))
// val dataw_a = Input(UInt(8.W))
// val dataw_b = Input(UInt(8.W))
} }
class MirrorSRAM extends BlackBox with HasBlackBoxInline { class MirrorSRAM extends BlackBox with HasBlackBoxInline {
val io: MirrorSRAM = IO(new MirrorSRAM) val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
setInline("lvds_bus_master.v", setInline("lvds_bus_master.v",
""" """
| module MirrorSRAM( | module MirrorSRAM(
| output [7:0] datar_a, | output [7:0] datar,
| output [7:0] datar_b, | input [7:0] dataw,
| |
| input clock, | input clock,
| input reset, | input reset,
| |
| input ce_a, | input we,
| input ce_b,
| |
| input we_a, | input [11:0] addrw,
| input we_b, | input [11:0] addrr
| |
| input [10:0] addr_a,
| input [10:0] addr_b,
|
| input [7:0] dataw_a
| input [7:0] dataw_b
| ); | );
| |
| wire [15:0] doa; | wire [31:0] dout;
| wire [15:0] dob; | assign datar = dout[7:0];
| |
| |
| assign datar_a = doa[7:0]; |SDPB bram_sdpb_0 (
| assign datar_b = dob[7:0]; | .DO({dout[31:8],dout[7:0]}),
| | .CLKA(clock),
| DPB bram_dpb_0 ( | .CEA(we),
| .DOA(doa), | .RESETA(reset),
| .DOB(dob), | .CLKB(clock),
| .CLKA(clock), | .CEB(1'b1),
| .OCEA(1'b1), | .RESETB(reset),
| .CEA(ce_a), | .OCE(1'b1),
| .RESETA(reset), | .BLKSELA(3'b0),
| .WREA(we_a), | .BLKSELB(3'b0),
| .CLKB(clock), | .ADA({addrw,3'b0}),
| .OCEB(1'b1), | .DI({24'b0, dataw}),
| .CEB(ce_b), | .ADB({addrr,3'b0})
| .RESETB(reset), | );
| .WREB( we_b ), | defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
| .BLKSELA(3'b0), | defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
| .BLKSELB(3'b0), | defparam bram_sdpb_0.RESET_MODE = "SYNC";
| .ADA({addr_a[10:0],3'b000}),
| .DIA({8'b0,dataw_a}),
| .ADB({addr_b[10:0],3'b000}),
| .DIB({8'b0,dataw_b})
| );
|
| defparam bram_dpb_0.READ_MODE0 = 1'b0;
| defparam bram_dpb_0.READ_MODE1 = 1'b0;
| defparam bram_dpb_0.WRITE_MODE0 = 2'b00;
| defparam bram_dpb_0.WRITE_MODE1 = 2'b00;
| defparam bram_dpb_0.BIT_WIDTH_0 = 8;
| defparam bram_dpb_0.BIT_WIDTH_1 = 8;
| defparam bram_dpb_0.RESET_MODE = "SYNC";
| |
| ); | );
|endmodule |endmodule

2
src/main/scala/backBoard/goWinBus.scala
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@@ -108,7 +108,7 @@ class Lvds_Bus_SlaveIO extends Bundle{
val lvds_up_dout = Output(Bool()) val lvds_up_dout = Output(Bool())
val downstream_rx_data_valid = Output(Bool()) val downstream_rx_data_valid = Output(Bool())
val downstream_rx_data_out = Ouyput(UInt(8.W)) val downstream_rx_data_out = Output(UInt(8.W))
val downstream_rx_crc_valid = Output(Bool()) val downstream_rx_crc_valid = Output(Bool())
val downstream_rx_crc_err = Output(Bool()) val downstream_rx_crc_err = Output(Bool())
val downstream_rx_crc_err_counter = Output(UInt(8.W)) val downstream_rx_crc_err_counter = Output(UInt(8.W))

0
src/main/scala/backBoard/FSMC.scala → src/main/scala/backBoard/trush/FSMC.scala.bk
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