slv

src/main/scala/backBoard/MirrorSRAM.scala

@@ -6,92 +6,85 @@ import chisel3.util._
 
 
 
+
+
+
+
+
 class MirrorSRAMIO extends Bundle{
+  val datar = Output(UInt(8.W))
+  val dataw = Input(UInt(8.W))
+  val clock = Input(Bool())
+  val reset = Input(Bool())
+  val we = Input(Bool())
+  val addrr = Input(UInt(11.W))
+  val addrw = Input(UInt(11.W))
 
-  val datar_a = Output(UInt(8.W))
-  val datar_b = Output(UInt(8.W))
 
-  val clk_a = Input(Bool())
-  val clk_b = Input(Bool())
+  // val datar_a = Output(UInt(8.W))
+  // val datar_b = Output(UInt(8.W))
 
-  val reset_a = Input(Bool())
-  val reset_b = Input(Bool())
+  // val clk_a = Input(Bool())
+  // val clk_b = Input(Bool())
 
-  val ce_a = Input(Bool())
-  val ce_b = Input(Bool())
+  // val reset_a = Input(Bool())
+  // val reset_b = Input(Bool())
 
-  val we_a = Input(Bool())
-  val we_b = Input(Bool())
+  // val ce_a = Input(Bool())
+  // val ce_b = Input(Bool())
 
-  val addr_a = Input(UInt(11.W))
-  val addr_b = Input(UInt(11.W))
+  // val we_a = Input(Bool())
+  // val we_b = Input(Bool())
 
-  val dataw_a = Input(UInt(8.W))
-  val dataw_b = Input(UInt(8.W))
+  // val addr_a = Input(UInt(11.W))
+  // val addr_b = Input(UInt(11.W))
+
+  // val dataw_a = Input(UInt(8.W))
+  // val dataw_b = Input(UInt(8.W))
 }
 
 class MirrorSRAM extends BlackBox with HasBlackBoxInline {
 
-  val io: MirrorSRAM = IO(new MirrorSRAM)
+  val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
 
   setInline("lvds_bus_master.v",
               """
   |   module MirrorSRAM(
-  |      output [7:0] datar_a,
-  |      output [7:0] datar_b,
+  |      output [7:0] datar,
+  |      input  [7:0] dataw,
   |
   |      input clock,
   |      input reset,
   |
-  |      input ce_a,
-  |      input ce_b,
+  |      input we,
   |
-  |      input we_a,
-  |      input we_b,
+  |      input [11:0] addrw,
+  |      input [11:0] addrr
   |
-  |      input [10:0] addr_a,
-  |      input [10:0] addr_b,
-  |
-  |      input [7:0] dataw_a
-  |      input [7:0] dataw_b
   |   );
   |
-  |   wire [15:0] doa; 
-  |   wire [15:0] dob; 
+  |   wire [31:0] dout; 
+  |   assign datar = dout[7:0];
   |
-
   |
-  |   assign datar_a = doa[7:0];
-  |   assign datar_b = dob[7:0];
-  |
-  |   DPB bram_dpb_0 (
-  |      .DOA(doa),
-  |      .DOB(dob),
-  |      .CLKA(clock),
-  |      .OCEA(1'b1),
-  |      .CEA(ce_a),
-  |      .RESETA(reset),
-  |      .WREA(we_a),
-  |      .CLKB(clock),
-  |      .OCEB(1'b1),
-  |      .CEB(ce_b),
-  |      .RESETB(reset),
-  |      .WREB( we_b ),
-  |      .BLKSELA(3'b0),
-  |      .BLKSELB(3'b0),
-  |      .ADA({addr_a[10:0],3'b000}),
-  |      .DIA({8'b0,dataw_a}),
-  |      .ADB({addr_b[10:0],3'b000}),
-  |      .DIB({8'b0,dataw_b})
-  |      );
-  |
-  |      defparam bram_dpb_0.READ_MODE0 = 1'b0;
-  |      defparam bram_dpb_0.READ_MODE1 = 1'b0;
-  |      defparam bram_dpb_0.WRITE_MODE0 = 2'b00;
-  |      defparam bram_dpb_0.WRITE_MODE1 = 2'b00;
-  |      defparam bram_dpb_0.BIT_WIDTH_0 = 8;
-  |      defparam bram_dpb_0.BIT_WIDTH_1 = 8;
-  |      defparam bram_dpb_0.RESET_MODE = "SYNC";
+  |SDPB bram_sdpb_0 (
+  |  .DO({dout[31:8],dout[7:0]}),
+  |  .CLKA(clock),
+  |  .CEA(we),
+  |  .RESETA(reset),
+  |  .CLKB(clock),
+  |  .CEB(1'b1),
+  |  .RESETB(reset),
+  |  .OCE(1'b1),
+  |  .BLKSELA(3'b0),
+  |  .BLKSELB(3'b0),
+  |  .ADA({addrw,3'b0}),
+  |  .DI({24'b0, dataw}),
+  |  .ADB({addrr,3'b0})
+  |  );
+  |  defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
+  |  defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
+  |  defparam bram_sdpb_0.RESET_MODE = "SYNC";
   |
   | );
   |endmodule