slv

2023-08-18 12:10:47 +00:00
parent 6fa2ef5f6e
commit f3a44f0b31
5 changed files with 339 additions and 110 deletions
--- a/src/main/scala/backBoard/BackBoardSlv.scala
+++ b/src/main/scala/backBoard/BackBoardSlv.scala
@@ -0,0 +1,139 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+class BackBoardSlvIO extends Bundle{
+  val reset     = Input(Bool())
+  val oser_pclk = Input(Bool())
+  val oser_fclk = Input(Bool())
+  val ides_pclk = Input(Bool())
+  val ides_fclk = Input(Bool())
+
+  val lvds_down_din  = Input(Bool())
+  val lvds_down_dout = Output(Bool())
+  val lvds_up_din    = Input(Bool())
+  val lvds_up_dout   = Output(Bool())
+}
+
+
+abstract class BackBoardSlvBase extends RawModule{
+  val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
+
+  val lvdsSlv = Module(new Lvds_Bus_Slave)
+
+  lvdsSlv.io.rst_n     := ~io.reset    
+  lvdsSlv.io.oser_pclk := io.oser_pclk
+  lvdsSlv.io.oser_fclk := io.oser_fclk
+  lvdsSlv.io.ides_pclk := io.ides_pclk
+  lvdsSlv.io.ides_fclk := io.ides_fclk
+  
+
+  lvdsSlv.io.lvds_down_din  := io.lvds_down_din 
+  lvdsSlv.io.lvds_down_dout := io.lvds_down_dout
+  lvdsSlv.io.lvds_up_din    := io.lvds_up_din   
+  lvdsSlv.io.lvds_up_dout   := io.lvds_up_dout  
+    
+  val downReg = Reg(Vec(32, UInt(8.W)))
+  val upReg   = Reg(Vec(32, UInt(8.W)))
+
+
+
+
+  // val downstream_rx_data_valid = Output(Bool())
+  // val downstream_rx_data_out   = Output(UInt(8.W))
+  // val downstream_rx_crc_valid  = Output(Bool())
+  // val downstream_rx_crc_err = Output(Bool())
+  // val downstream_rx_crc_err_counter = Output(UInt(8.W))
+  // val downstream_rx_cdr_err = Output(Bool())
+  // val downstream_sync = Output(Bool())
+
+  val upstream_tx_data_ready = Output(Bool())
+  val upstream_tx_data_in = Input(UInt(8.W))
+
+  // val upstream_rx_crc_valid = Output(Bool())
+  // val upstream_rx_crc_err = Output(Bool())
+  // val upstream_rx_crc_err_counter = Output(UInt(8.W))
+  // val upstream_rx_cdr_err = Output(Bool())
+}
+
+
+trait BackBoardSlvDown{ this: BackBoardSlvBase =>
+
+  withClockAndReset( io.ides_pclk.asClock, io.reset ){
+    val downCnt = RegInit(0.U(6.W))
+    val downTimeoutEn  = RegInit( false.B )
+    val downTimeoutRst = (downCnt === 0.U & downstream_rx_data_valid)
+    val ( _, downTimeout ) = Counter( Range( 0,1023 ), downTimeoutEn, downTimeoutRst )
+
+
+    when( io.reset ){
+      for( i <- 0 until 32 ){
+        downReg(i) := 0.U
+      }
+    } .otherwise{
+      when( downstream_rx_data_valid ){
+        downReg(downCnt) := downstream_rx_data_out
+      }
+    }
+
+    when( downTimeout ){
+      downTimeoutEn := false.B
+    } .elsewhen( downCnt === 32.U ){
+      downTimeoutEn := false.B
+    } .elsewhen(downCnt === 0.U & downstream_rx_data_valid){
+      downTimeoutEn := true.B
+    }
+
+    when( downTimeout ){
+      downCnt := 0.U
+    }.elsewhen( downCnt === 32.U ){
+      downCnt := 0.U
+    }.elsewhen( downstream_rx_data_valid ){
+      downCnt := downCnt + 1.U
+    }
+
+  }
+}
+
+trait BackBoardSlvUp{ this: BackBoardSlvBase =>
+
+  withClockAndReset( io.ides_pclk.asClock, io.reset ){
+    val upCnt = RegInit(0.U(6.W))
+    val upTimeoutEn  = RegInit( false.B )
+    val upTimeoutRst = (upCnt === 0.U & upstream_tx_data_ready)
+    val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
+
+      // when( upstream_tx_data_ready ){
+      //   upstream_tx_data_ready := upReg(upCnt)
+      // }
+
+    when( io.reset ){
+      for( i <- 0 until 32 ){
+        upReg(i) := 0.U
+      }
+    } .otherwise{
+
+    }
+
+    when( upTimeout ){
+      upTimeoutEn := false.B
+    } .elsewhen( upCnt === 32.U ){
+      upTimeoutEn := false.B
+    } .elsewhen(upCnt === 0.U & upstream_tx_data_ready){
+      upTimeoutEn := true.B
+    }
+
+    when( upTimeout ){
+      upCnt := 0.U
+    }.elsewhen( upCnt === 32.U ){
+      upCnt := 0.U
+    }.elsewhen( upstream_tx_data_ready ){
+      upCnt := upCnt + 1.U
+    }
+
+  }
+}
+