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This commit is contained in:
Ruige Lee
2023-08-18 12:10:47 +00:00
parent 6fa2ef5f6e
commit f3a44f0b31
5 changed files with 339 additions and 110 deletions
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195
src/main/scala/backBoard/BackBoardMst.scala
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@@ -29,55 +29,67 @@ class BackBoardMstIO extends Bundle{
}
class BackBoardMstBase extends Module{
class BackBoardMstBase extends RawModule{
val io: BackBoardMstIO = IO(new BackBoardMstIO)
val fsmcSlv = Module(new FSMCSlv)
fsmcSlv.io.FSMC <> io.FSMC
val lvdsMst = Module(new Lvds_Bus_Master)
val mirrorDown = Module(new MirrorSRAM)
val mirrorUp = Module(new MirrorSRAM)
val status = Reg(UInt(8.W))
val slvNum = Reg(UInt(5.W))
val ( cnt, trigger ) = Counter(Range( 0,1023))
val status = RegInit(0.U(8.W))
val slvNum = RegInit(0.U(6.W))
val mirror = Module(new MirrorSRAM)
mirror.io.clock := io.ides_pclk.asBool
mirror.io.reset := io.reset.asBool
mirrorDown.io.clock := io.ides_pclk.asBool
mirrorDown.io.reset := io.reset.asBool
mirrorUp.io.clock := io.ides_pclk.asBool
mirrorUp.io.reset := io.reset.asBool
}
trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B )
val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B )
val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B )
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B )
val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B )
val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B )
io.FSMC.dataOEn := io.FSMC.oen
io.FSMC.dataOEn := io.FSMC.oen
mirrorDown.io.we := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
mirrorDown.io.addrw := fsmcAddrSync(10,0)
mirrorDown.io.dataw := fsmcdataInSync
// mirrorUp.io.ce := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
mirrorUp.io.addrr := fsmcAddrSync(10,0)
val regOut = Wire(UInt(8.W))
io.FSMC.dataOut := mirror.io.datar_a
mirror.io.ce_a := (~fsmcCEnSync & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync | ~fsmcWEnSync) )
mirror.io.we_a := ~fsmcWEnSync
mirror.io.addr_a := fsmcAddrSync(10,0)
mirror.io.dataw_a := fsmcdataInSync
io.FSMC.dataOut := Mux( fsmcAddrSync.extract(12), regOut, mirrorUp.io.datar)
regOut := Mux1H(Seq(
(fsmcAddrSync(10,0) === 0.U) -> status,
(fsmcAddrSync(10,0) === 1.U) -> slvNum,
))
when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 0.U) ){
status := fsmcdataInSync
}
when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 1.U) ){
slvNum := fsmcdataInSync
}
}
}
@@ -94,29 +106,114 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
lvdsMst.io.tx_start := false.B
.elsewhen( cnt === 0.U ){
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val stateCur = RegInit(0.U(3.W))
val ( cnt, trigger ) = Counter(Range( 0,1023))
val addrr = RegInit(0.U)
val addrw = RegInit(0.U)
when( trigger ){
stateCur := 0.U
addrr := 0.U
addrw := 0.U
lvdsMst.io.frame_info_update_en := true.B
lvdsMst.io.slave_type_num := Cat( "b000".U(3.W), slvNum )
lvdsMst.io.slave_data_length := (8/8*4*8-1).U
lvdsMst.io.tx_start := false.B
} .elsewhen( stateCur === 0.U ){
stateCur := 1.U
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := true.B
} .elsewhen( stateCur === 1.U ){
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
stateCur := 2.U
}
} .elsewhen( stateCur === 2.U ){
stateCur := 3.U
lvdsMst.io.frame_info_update_en := true.B
lvdsMst.io.slave_type_num := Cat( "b10".U(2.W), 0.U(6.W) )
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
addrr := 0.U
addrw := 0.U
} .elsewhen( stateCur === 3.U ){
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := true.B
} .elsewhen( stateCur === 4.U ){
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
when( lvdsMst.io.tx_data_ready ){
addrr := addrr + 1.U
}
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
stateCur := 5.U
}
} .elsewhen( stateCur === 5.U ){
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
} .otherwise{
lvdsMst.io.frame_info_update_en := false.B
lvdsMst.io.slave_type_num := 0.U
lvdsMst.io.slave_data_length := 0.U
lvdsMst.io.tx_start := false.B
assert(false.B)
}
when( lvdsMst.io.rx_data_valid ){
assert( (stateCur === 4.U) || (stateCur === 5.U) )
addrw := addrw + 1.U
}
lvdsMst.io.tx_data_in := mirrorDown.io.datar
mirrorDown.io.addrr := addrr
} .elsewhen( cnt === 1.U ){
lvdsMst.io.tx_start := true.B
mirrorUp.io.we := lvdsMst.io.rx_data_valid
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
mirrorUp.io.addrw := addrw
}
lvdsMst.io.frame_info_update_en := (cnt === 0.U)
lvdsMst.io.slave_type_num := Cat( "b00".U(2.W), slvNum )
lvdsMst.io.slave_data_length := (8/8*4*8-1).U
lvdsMst.io.tx_start = Input(Bool())
lvdsMst.io.tx_data_in = Input(UInt(8.W))
lvdsMst.io.tx_data_ready = Output(Bool())
lvdsMst.io.downstream_busy = Output(Bool())
lvdsMst.io.rx_data_out = Output(UInt(8.W))
lvdsMst.io.rx_data_valid = Output(Bool())
lvdsMst.io.upstream_crc_valid = Output(Bool())
lvdsMst.io.upstream_crc_err = Output(Bool())
lvdsMst.io.upstream_crc_err_count = Output(UInt(8.W))
lvdsMst.io.upstream_cdr_err = Output(Bool())
}