调整同步，允许主站产生sync0，1，2，3信号

src/main/scala/backBoard/shin/Interface.scala

@@ -77,9 +77,12 @@ class CommonRegisterBundle extends Bundle{
 
   val timeStamp = UInt(64.W)
   val mstDeltaTime = UInt(32.W)
-
+  val syncCfg = UInt(8.W)
+  val syncWidth  = Vec(4, UInt(16.W) )
+  val syncOffset = Vec(4, UInt(32.W))
   val syncPoint = UInt(64.W)
   val syncPeroid = UInt(32.W)
+  val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
 
   val custom = Vec( 128, UInt(8.W) )
 
@@ -120,12 +123,9 @@ class SlaveRegisterBundle extends Bundle{
 
   val slvDeltaTime  = UInt(32.W) //从站时间戳差值
   val deltaFinal    = UInt(32.W) //当前时间戳与主站时间差
-  val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
 
-  val syncCfg = UInt(8.W)
-  val syncWidth = Vec(4, UInt(16.W) )
 
-  val syncOffset = Vec(4, UInt(32.W))
+
 
 }
 
@@ -208,20 +208,7 @@ abstract class InterfaceBase extends Module{
   val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
   val sReg = Wire(new SlaveRegisterBundle);  io.sReg := sReg
 
-  val syncCfg = RegInit(0.U(8.W)); sReg.syncCfg := syncCfg
 
-  val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
-  for( i <- 0 until 4 ) {
-    sReg.syncWidth(i) := syncWidth(i)
-  }
-
-  val syncPoint   = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
-  val syncPeroid  = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
-
-  val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
-  for( i <- 0 until 4 ) {
-    sReg.syncOffset(i) := syncOffset(i)
-  }
 
 
 
@@ -378,28 +365,28 @@ abstract class InterfaceBase extends Module{
         (addr === "h117".U & isSlvMode)  -> sReg.slvDeltaTime(31,24),
 
         //校准后的时钟
-        (addr === "h118".U & isSlvMode)  -> sReg.recoTimeStamp(7,0),
+        (addr === "h118".U )  -> cReg.recoTimeStamp(7,0),
-        (addr === "h119".U & isSlvMode)  -> sReg.recoTimeStamp(15,8),
+        (addr === "h119".U )  -> cReg.recoTimeStamp(15,8),
-        (addr === "h11a".U & isSlvMode)  -> sReg.recoTimeStamp(23,16),
+        (addr === "h11a".U )  -> cReg.recoTimeStamp(23,16),
-        (addr === "h11b".U & isSlvMode)  -> sReg.recoTimeStamp(31,24),
+        (addr === "h11b".U )  -> cReg.recoTimeStamp(31,24),
-        (addr === "h11c".U & isSlvMode)  -> sReg.recoTimeStamp(39,32),
+        (addr === "h11c".U )  -> cReg.recoTimeStamp(39,32),
-        (addr === "h11d".U & isSlvMode)  -> sReg.recoTimeStamp(47,40),
+        (addr === "h11d".U )  -> cReg.recoTimeStamp(47,40),
-        (addr === "h11e".U & isSlvMode)  -> sReg.recoTimeStamp(55,48),
+        (addr === "h11e".U )  -> cReg.recoTimeStamp(55,48),
-        (addr === "h11f".U & isSlvMode)  -> sReg.recoTimeStamp(63,56),
+        (addr === "h11f".U )  -> cReg.recoTimeStamp(63,56),
 
-        (addr === "h120".U & isSlvMode)  -> sReg.syncCfg,
+        (addr === "h120".U )  -> cReg.syncCfg,
 
-        (addr === "h122".U & isSlvMode)  -> sReg.syncWidth(0)(7,0),
+        (addr === "h122".U )  -> cReg.syncWidth(0)(7,0),
-        (addr === "h123".U & isSlvMode)  -> sReg.syncWidth(0)(15,8),
+        (addr === "h123".U )  -> cReg.syncWidth(0)(15,8),
 
-        (addr === "h124".U & isSlvMode)  -> sReg.syncWidth(1)(7,0),
+        (addr === "h124".U )  -> cReg.syncWidth(1)(7,0),
-        (addr === "h125".U & isSlvMode)  -> sReg.syncWidth(1)(15,8),
+        (addr === "h125".U )  -> cReg.syncWidth(1)(15,8),
 
-        (addr === "h126".U & isSlvMode)  -> sReg.syncWidth(2)(7,0),
+        (addr === "h126".U )  -> cReg.syncWidth(2)(7,0),
-        (addr === "h127".U & isSlvMode)  -> sReg.syncWidth(2)(15,8),
+        (addr === "h127".U )  -> cReg.syncWidth(2)(15,8),
 
-        (addr === "h128".U & isSlvMode)  -> sReg.syncWidth(3)(7,0),
+        (addr === "h128".U )  -> cReg.syncWidth(3)(7,0),
-        (addr === "h129".U & isSlvMode)  -> sReg.syncWidth(3)(15,8),
+        (addr === "h129".U )  -> cReg.syncWidth(3)(15,8),
 
         (addr === "h130".U )  -> cReg.syncPoint(7,0),
         (addr === "h131".U )  -> cReg.syncPoint(15,8),
@@ -415,20 +402,20 @@ abstract class InterfaceBase extends Module{
         (addr === "h13a".U )  -> cReg.syncPeroid(23,16),
         (addr === "h13b".U )  -> cReg.syncPeroid(31,24),
 
-        (addr === "h13c".U & isSlvMode)  -> sReg.syncOffset(1)(7,0),
+        (addr === "h13c".U )  -> cReg.syncOffset(1)(7,0),
-        (addr === "h13d".U & isSlvMode)  -> sReg.syncOffset(1)(15,8),
+        (addr === "h13d".U )  -> cReg.syncOffset(1)(15,8),
-        (addr === "h13e".U & isSlvMode)  -> sReg.syncOffset(1)(23,16),
+        (addr === "h13e".U )  -> cReg.syncOffset(1)(23,16),
-        (addr === "h13f".U & isSlvMode)  -> sReg.syncOffset(1)(31,24),
+        (addr === "h13f".U )  -> cReg.syncOffset(1)(31,24),
 
-        (addr === "h140".U & isSlvMode)  -> sReg.syncOffset(2)(7,0),
+        (addr === "h140".U )  -> cReg.syncOffset(2)(7,0),
-        (addr === "h141".U & isSlvMode)  -> sReg.syncOffset(2)(15,8),
+        (addr === "h141".U )  -> cReg.syncOffset(2)(15,8),
-        (addr === "h142".U & isSlvMode)  -> sReg.syncOffset(2)(23,16),
+        (addr === "h142".U )  -> cReg.syncOffset(2)(23,16),
-        (addr === "h143".U & isSlvMode)  -> sReg.syncOffset(2)(31,24),
+        (addr === "h143".U )  -> cReg.syncOffset(2)(31,24),
 
-        (addr === "h144".U & isSlvMode)  -> sReg.syncOffset(3)(7,0),
+        (addr === "h144".U )  -> cReg.syncOffset(3)(7,0),
-        (addr === "h145".U & isSlvMode)  -> sReg.syncOffset(3)(15,8),
+        (addr === "h145".U )  -> cReg.syncOffset(3)(15,8),
-        (addr === "h146".U & isSlvMode)  -> sReg.syncOffset(3)(23,16),
+        (addr === "h146".U )  -> cReg.syncOffset(3)(23,16),
-        (addr === "h147".U & isSlvMode)  -> sReg.syncOffset(3)(31,24),
+        (addr === "h147".U )  -> cReg.syncOffset(3)(31,24),
       ) ++
       ( 0 until 128 ).map{ i =>
         ( addr === ("h180".U(16.W) + i.U )   ) -> cReg.custom(i)
@@ -615,59 +602,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   }
 
 
-  when( isEnW & isSlvMode ){
-    when( addrw === "h120".U ){
-      syncCfg := dataw
-    }
 
-    for( i <- 0 until 4 ){
-      when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
-        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
-      } .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
-        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
-      }
-    }
-
-    when( addrw === "h130".U ){
-      syncPoint := Cat( syncPoint(63,8), dataw ) 
-    } .elsewhen( addrw === "h131".U ){
-      syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) ) 
-    } .elsewhen( addrw === "h132".U ){
-      syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) ) 
-    } .elsewhen( addrw === "h133".U ){
-      syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) ) 
-    } .elsewhen( addrw === "h134".U ){
-      syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) ) 
-    } .elsewhen( addrw === "h135".U ){
-      syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) ) 
-    } .elsewhen( addrw === "h136".U ){
-      syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) ) 
-    } .elsewhen( addrw === "h137".U ){
-      syncPoint := Cat( dataw, syncPoint(55,0) ) 
-    }
-
-    .elsewhen( addrw === "h138".U ){
-      syncPeroid := Cat( syncPeroid(31,8), dataw ) 
-    } .elsewhen( addrw === "h139".U ){
-      syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) ) 
-    } .elsewhen( addrw === "h13a".U ){
-      syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) ) 
-    } .elsewhen( addrw === "h13b".U ){
-      syncPeroid := Cat( dataw, syncPeroid(23,0) ) 
-    }
-
-    for( i <- 1 until 4 ){
-      when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
-        syncOffset(i) := Cat( syncOffset(i)(31,8), dataw ) 
-      } .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
-        syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) ) 
-      } .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
-        syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) ) 
-      } .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
-        syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) ) 
-      }      
-    }
-  }
 
 
 
@@ -747,6 +682,107 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
   
   io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
 
+
+  ( 0 until 8 ).map{ i =>
+    sReg.ebmmu(i).lAddr := Cat(
+      RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).pAddr := Cat(
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).length := Cat(
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).op :=
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
+
+    sReg.ebmmu(i).isEnable :=
+      RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
+  }
+
+}
+
+trait InterfaceSync{ this: InterfaceBase =>
+
+  val syncCfg = RegInit(0.U(8.W)); cReg.syncCfg := syncCfg
+
+  val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
+  for( i <- 0 until 4 ) {
+    cReg.syncWidth(i) := syncWidth(i)
+  }
+
+  val syncPoint   = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
+  val syncPeroid  = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
+
+  val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
+  for( i <- 0 until 4 ) {
+    cReg.syncOffset(i) := syncOffset(i)
+  }
+
+  when( isEnW & isSlvMode ){
+    when( addrw === "h120".U ){
+      syncCfg := dataw
+    }
+
+    for( i <- 0 until 4 ){
+      when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
+        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
+      } .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
+        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
+      }
+    }
+
+    when( addrw === "h130".U ){
+      syncPoint := Cat( syncPoint(63,8), dataw ) 
+    } .elsewhen( addrw === "h131".U ){
+      syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) ) 
+    } .elsewhen( addrw === "h132".U ){
+      syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) ) 
+    } .elsewhen( addrw === "h133".U ){
+      syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) ) 
+    } .elsewhen( addrw === "h134".U ){
+      syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) ) 
+    } .elsewhen( addrw === "h135".U ){
+      syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) ) 
+    } .elsewhen( addrw === "h136".U ){
+      syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) ) 
+    } .elsewhen( addrw === "h137".U ){
+      syncPoint := Cat( dataw, syncPoint(55,0) ) 
+    }
+
+    .elsewhen( addrw === "h138".U ){
+      syncPeroid := Cat( syncPeroid(31,8), dataw ) 
+    } .elsewhen( addrw === "h139".U ){
+      syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) ) 
+    } .elsewhen( addrw === "h13a".U ){
+      syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) ) 
+    } .elsewhen( addrw === "h13b".U ){
+      syncPeroid := Cat( dataw, syncPeroid(23,0) ) 
+    }
+
+    for( i <- 1 until 4 ){
+      when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,8), dataw ) 
+      } .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) ) 
+      } .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) ) 
+      } .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) ) 
+      }      
+    }
+  }
+
+
+
   when( io.lvds.isEnW & isSlvMode ){
 
     when( io.lvds.addrw === "h120".U ){
@@ -802,43 +838,15 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
     }
   }
 
-
-  ( 0 until 8 ).map{ i =>
-    sReg.ebmmu(i).lAddr := Cat(
-      RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
-      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
-      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
-      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
-    )
-
-    sReg.ebmmu(i).pAddr := Cat(
-      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
-      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
-    )
-
-    sReg.ebmmu(i).length := Cat(
-      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
-      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
-    )
-
-    sReg.ebmmu(i).op :=
-      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
-
-    sReg.ebmmu(i).isEnable :=
-      RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
-  }
-
-}
-
-trait InterfaceSync{ this: InterfaceBase =>
   cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
-
   cReg.mstDeltaTime := io.mstDeltaTime
 
 
-  // sReg.mstTimeStamp := io.mstTimeStamp
   sReg.deltaFinal := io.deltaFinal
-  sReg.recoTimeStamp := RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
+  cReg.recoTimeStamp := 
+    Mux(isMstMode, cReg.timeStamp,
+      RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
+    )
   sReg.slvDeltaTime := io.slvDeltaTime
   
   val syncSign = for( i <- 0 until 4 ) yield { RegInit(false.B) }
@@ -846,53 +854,49 @@ trait InterfaceSync{ this: InterfaceBase =>
   val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
 
 
-  when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
+  when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
     syncSign(0) := true.B
     syncPoint := syncPoint + cReg.syncPeroid
-  } .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){
+  } .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
     syncSign(0) := false.B
-  } .elsewhen( sReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
+  } .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
     syncSign(0) := false.B
   }
 
   for( i <- 1 until 4 ) {
 
-    when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
+    when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
       syncOffsetCnt(i) := 0.U
-    } .elsewhen( syncOffsetCnt(i) < sReg.syncOffset(i) ){
+    } .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){
       syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
-    } .elsewhen( syncOffsetCnt(i) === sReg.syncOffset(i) ){
+    } .elsewhen( syncOffsetCnt(i) === cReg.syncOffset(i) ){
       syncOffsetCnt(i) := "hFFFFFFFF".U(32.W)
     }
 
-    when( syncOffsetCnt(i) === sReg.syncOffset(i) ){
+    when( syncOffsetCnt(i) === cReg.syncOffset(i) ){
       syncSign(i) := true.B
-    } .elsewhen( ~sReg.syncCfg(4+i) & syncResetCnt(i) === sReg.syncWidth(i) ){
+    } .elsewhen( ~cReg.syncCfg(4+i) & syncResetCnt(i) === cReg.syncWidth(i) ){
       syncSign(i) := false.B
-    } .elsewhen( sReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
+    } .elsewhen( cReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
       syncSign(i) := false.B
     }
 
   }
 
   for( i <- 0 until 4 ){
-    when( ~sReg.syncCfg(4+i) ){
+    when( ~cReg.syncCfg(4+i) ){
       when( syncSign(i) ){
         syncResetCnt(i) := syncResetCnt(i) + 1.U
       } .otherwise{
         syncResetCnt(i) := 0.U
       }
     }
-
   }
 
-
+  io.sync(0) := cReg.syncCfg.extract(0) & syncSign(0)
-
+  io.sync(1) := cReg.syncCfg.extract(1) & syncSign(1)
-
+  io.sync(2) := cReg.syncCfg.extract(2) & syncSign(2)
-  io.sync(0) := sReg.syncCfg.extract(0) & syncSign(0) & isSlvMode
+  io.sync(3) := cReg.syncCfg.extract(3) & syncSign(3)
-  io.sync(1) := sReg.syncCfg.extract(1) & syncSign(1) & isSlvMode
-  io.sync(2) := sReg.syncCfg.extract(2) & syncSign(2) & isSlvMode
-  io.sync(3) := sReg.syncCfg.extract(3) & syncSign(3) & isSlvMode
 
 }