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RuigeLee
2024-06-25 18:40:53 +08:00
parent 3406a418d1
commit f32e82cd7b
1 changed files with 13 additions and 12 deletions
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25
src/main/scala/backBoard/Qei.scala
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@@ -8,7 +8,7 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
val phaseA = for( i <- 0 until 2 ) yield { Wire(Bool()) } val phaseA = for( i <- 0 until 2 ) yield { Wire(Bool()) }
val phaseB = for( i <- 0 until 2 ) yield { Wire(Bool()) } val phaseB = for( i <- 0 until 2 ) yield { Wire(Bool()) }
val phaseZ = for( i <- 0 until 2 ) yield { Wire(Bool()) } val phaseZ = for( i <- 0 until 2 ) yield { Wire(Bool()) }
val counter = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) } val counter = for( i <- 0 until 2 ) yield { Reg(UInt(33.W)) }
val encordNxt = for( i <- 0 until 2 ) yield { Cat( phaseB(i), phaseA(i) ) } val encordNxt = for( i <- 0 until 2 ) yield { Cat( phaseB(i), phaseA(i) ) }
val encordCur = for( i <- 0 until 2 ) yield { RegNext(encordNxt(i)) } val encordCur = for( i <- 0 until 2 ) yield { RegNext(encordNxt(i)) }
@@ -23,8 +23,6 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
val isSetValPos = for( i <- 0 until 2 ) yield { ~RegNext( isSetVal(i), false.B ) & isSetVal(i) } val isSetValPos = for( i <- 0 until 2 ) yield { ~RegNext( isSetVal(i), false.B ) & isSetVal(i) }
val isSetValNeg = for( i <- 0 until 2 ) yield { RegNext( isSetVal(i), false.B ) & ~isSetVal(i) } val isSetValNeg = for( i <- 0 until 2 ) yield { RegNext( isSetVal(i), false.B ) & ~isSetVal(i) }
val isAdvA = for( i <- 0 until 2 ) yield { val isAdvA = for( i <- 0 until 2 ) yield {
( encordCur(i) === "b00".U & encordNxt(i) === "b01".U & mode(i).extract(1)) | ( encordCur(i) === "b00".U & encordNxt(i) === "b01".U & mode(i).extract(1)) |
( encordCur(i) === "b01".U & encordNxt(i) === "b11".U & mode(i) =/= "b00".U ) | ( encordCur(i) === "b01".U & encordNxt(i) === "b11".U & mode(i) =/= "b00".U ) |
@@ -44,6 +42,9 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
// val isKeep = for( i <- 0 until 2 ) yield { encordCur(i) === encordNxt(i) } // val isKeep = for( i <- 0 until 2 ) yield { encordCur(i) === encordNxt(i) }
val isOverflow = for( i <- 0 until 2 ) yield { Wire(Bool()) } val isOverflow = for( i <- 0 until 2 ) yield { Wire(Bool()) }
val isCounter32Flip = for( i <- 0 until 2 ) yield { RegNext( counter(i).extract(32)) =/= counter(i).extract(32) }
val isCounter31Flip = for( i <- 0 until 2 ) yield { RegNext( counter(i).extract(31)) =/= counter(i).extract(31) }
for( i <- 0 until 2 ){ for( i <- 0 until 2 ){
@@ -60,7 +61,7 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
when(isEnable(i)){ when(isEnable(i)){
when(~is2Phase(i)){ //A Phase only when(~is2Phase(i)){ //A Phase only
when( RegNext( phaseA(i) ) & ~phaseA(i) ){ when( RegNext( phaseA(i) ) & ~phaseA(i) ){
when( isSetVal(i) & counter(i) === "hFFFFFFFF".U ){ when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) + 1.U counter(i) := counter(i) + 1.U
@@ -72,13 +73,13 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
} .elsewhen( isAdvA(i) ){ } .elsewhen( isAdvA(i) ){
when( isSign(i) ) { when( isSign(i) ) {
when( invDirect(i) ){ when( invDirect(i) ){
when( isSetVal(i) & counter(i) === "h80000000".U ){ when( isSetVal(i) & isCounter31Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) - 1.U counter(i) := counter(i) - 1.U
} }
} .otherwise{ } .otherwise{
when( isSetVal(i) & counter(i) === "h7FFFFFFF".U ){ when( isSetVal(i) & isCounter31Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) + 1.U counter(i) := counter(i) + 1.U
@@ -86,13 +87,13 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
} }
} .otherwise{ } .otherwise{
when( invDirect(i) ){ when( invDirect(i) ){
when( isSetVal(i) & counter(i) === 0.U ){ when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) - 1.U counter(i) := counter(i) - 1.U
} }
} .otherwise{ } .otherwise{
when( isSetVal(i) & counter(i) === "hFFFFFFFF".U ){ when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) + 1.U counter(i) := counter(i) + 1.U
@@ -102,13 +103,13 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
} .elsewhen( isAdvB(i) ){ } .elsewhen( isAdvB(i) ){
when( isSign(i) ) { when( isSign(i) ) {
when( invDirect(i) ){ when( invDirect(i) ){
when( isSetVal(i) & counter(i) === "h7FFFFFFF".U ){ when( isSetVal(i) & isCounter31Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) + 1.U counter(i) := counter(i) + 1.U
} }
} .otherwise{ } .otherwise{
when( isSetVal(i) & counter(i) === "h80000000".U ){ when( isSetVal(i) & isCounter31Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) - 1.U counter(i) := counter(i) - 1.U
@@ -116,13 +117,13 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
} }
} .otherwise{ } .otherwise{
when( invDirect(i) ){ when( invDirect(i) ){
when( isSetVal(i) & counter(i) === "hFFFFFFFF".U ){ when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) + 1.U counter(i) := counter(i) + 1.U
} }
} .otherwise{ } .otherwise{
when( isSetVal(i) & counter(i) === 0.U ){ when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B isOverflow(i) := true.B
} .otherwise{ } .otherwise{
counter(i) := counter(i) - 1.U counter(i) := counter(i) - 1.U