diff --git a/doc/spec/物理层优化.md b/doc/spec/物理层优化.md
index abb6d23..eeabb5f 100644
--- a/doc/spec/物理层优化.md
+++ b/doc/spec/物理层优化.md
@@ -43,6 +43,10 @@
 
 * 主站寄存器增加"h600"指向CDR_OUT的ctrlWord
 
+* 从站SlaveParse层增加两个`ctrlWordRelay`寄存器，
+    - 下行relay只看下行输入的6个`isK`布尔信号直接转译8bit原始码
+    - 上行relay在`isProbeAck`跳变状态直接拷贝下行寄存器信息，其它条件看上行输入的6个`isK`布尔信号直接转译8bit原始码
+
 
 ---------------------------------------
 
diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
index 9696ba1..1a0aa69 100644
--- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala
+++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
@@ -75,9 +75,6 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   interface.io.intTransEnd(2) := upCDRInAxis.io.axis.fire    & upCDRInAxis.io.axis.bits.tlast
   interface.io.intTransEnd(3) := upCDROut.io.axis.fire   & upCDROut.io.axis.bits.tlast
   
-  downCDROut.io.ctrlWord := interface.io.mReg.ctrlWord
-  upCDROut.io.ctrlWord   := interface.io.mReg.ctrlWord
-
   io.isSoftReset := interface.io.isSoftReset
   io.interrupt   := interface.io.interrupt
 
@@ -245,6 +242,9 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
     upCDROut.io.axis.valid := false.B
     upCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
 
+    downCDROut.io.ctrlWord := 0.U
+    upCDROut.io.ctrlWord   := 0.U
+
     interface.io.mstDeltaTime := 0.U
 
     interface.io.slvDeltaTime := 0.U
@@ -267,6 +267,20 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
 
     interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
     interface.io.upRecStat   := 0.U.asTypeOf(new Stat_IO_Bundle)
+
+    slaveParser.io.downCtrlWordIsK28_0 := false.B
+    slaveParser.io.downCtrlWordIsK28_3 := false.B
+    slaveParser.io.downCtrlWordIsK28_4 := false.B
+    slaveParser.io.downCtrlWordIsK28_1 := false.B
+    slaveParser.io.downCtrlWordIsK28_2 := false.B
+    slaveParser.io.downCtrlWordIsK28_6 := false.B
+
+    slaveParser.io.upCtrlWordIsK28_0   := false.B
+    slaveParser.io.upCtrlWordIsK28_3   := false.B
+    slaveParser.io.upCtrlWordIsK28_4   := false.B
+    slaveParser.io.upCtrlWordIsK28_1   := false.B
+    slaveParser.io.upCtrlWordIsK28_2   := false.B
+    slaveParser.io.upCtrlWordIsK28_6   := false.B
   }
 
 }
@@ -325,6 +339,9 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
     interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
     interface.io.upRecStat   := masterParser.io.upRecStat
 
+    downCDROut.io.ctrlWord := interface.io.mReg.ctrlWord
+    upCDROut.io.ctrlWord   := interface.io.mReg.ctrlWord
+
   }
 
   masterParser.io.req         := interface.io.txReq.valid
@@ -399,6 +416,23 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
     interface.io.downRecStat := slaveParser.io.downRecStat
     interface.io.upRecStat   := slaveParser.io.upRecStat
 
+    downCDROut.io.ctrlWord := slaveParser.io.downCtrlWordRelay
+    upCDROut.io.ctrlWord   := slaveParser.io.upCtrlWordRelay
+
+    slaveParser.io.downCtrlWordIsK28_0 := downCDRInAxis.io.isK28_0
+    slaveParser.io.downCtrlWordIsK28_3 := downCDRInAxis.io.isK28_3
+    slaveParser.io.downCtrlWordIsK28_4 := downCDRInAxis.io.isK28_4
+    slaveParser.io.downCtrlWordIsK28_1 := downCDRInAxis.io.isK28_1
+    slaveParser.io.downCtrlWordIsK28_2 := downCDRInAxis.io.isK28_2
+    slaveParser.io.downCtrlWordIsK28_6 := downCDRInAxis.io.isK28_6
+
+    slaveParser.io.upCtrlWordIsK28_0   := upCDRInAxis.io.isK28_0
+    slaveParser.io.upCtrlWordIsK28_3   := upCDRInAxis.io.isK28_3
+    slaveParser.io.upCtrlWordIsK28_4   := upCDRInAxis.io.isK28_4
+    slaveParser.io.upCtrlWordIsK28_1   := upCDRInAxis.io.isK28_1
+    slaveParser.io.upCtrlWordIsK28_2   := upCDRInAxis.io.isK28_2
+    slaveParser.io.upCtrlWordIsK28_6   := upCDRInAxis.io.isK28_6
+
   }
 
   slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index c4824e4..48f3a5f 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -66,6 +66,23 @@ class SlaveParserIO extends Bundle{
 
   val downRecStat = Output(new Stat_IO_Bundle)
   val upRecStat   = Output(new Stat_IO_Bundle)
+
+  val downCtrlWordRelay = Output( UInt(8.W) )
+  val upCtrlWordRelay   = Output( UInt(8.W) )
+
+  val downCtrlWordIsK28_0  = Input(Bool()) //0x1c
+  val downCtrlWordIsK28_3  = Input(Bool()) //0x7c
+  val downCtrlWordIsK28_4  = Input(Bool()) //0x9c
+  val downCtrlWordIsK28_1  = Input(Bool()) //0x3c
+  val downCtrlWordIsK28_2  = Input(Bool()) //0x5c
+  val downCtrlWordIsK28_6  = Input(Bool()) //0xdc
+
+  val upCtrlWordIsK28_0  = Input(Bool()) //0x1c
+  val upCtrlWordIsK28_3  = Input(Bool()) //0x7c
+  val upCtrlWordIsK28_4  = Input(Bool()) //0x9c
+  val upCtrlWordIsK28_1  = Input(Bool()) //0x3c
+  val upCtrlWordIsK28_2  = Input(Bool()) //0x5c
+  val upCtrlWordIsK28_6  = Input(Bool()) //0xdc
 }
 
 abstract class SlaveParserBase extends Module with RequireAsyncReset{
@@ -116,7 +133,8 @@ abstract class SlaveParserBase extends Module with RequireAsyncReset{
 
   val localDevIndex = RegInit(0.U(14.W)); io.localDevIndex := localDevIndex //当前设备索引
 
-
+  val downCtrlWordRelay = RegInit("h1c".U); io.downCtrlWordRelay := downCtrlWordRelay
+  val upCtrlWordRelay = RegInit("h1c".U);   io.upCtrlWordRelay   := upCtrlWordRelay
 
 
 
@@ -1020,6 +1038,44 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
 
 }
 
+trait SlaveParserCtrlWord{ this: SlaveParserBase =>
+
+  val downCtrlWordRelay = Output( UInt(8.W) )
+  val upCtrlWordRelay   = Output( UInt(8.W) )
+
+  when( io.downCtrlWordIsK28_0 ){
+    downCtrlWordRelay := "h1c".U
+  } .elsewhen( io.downCtrlWordIsK28_3 ){
+    downCtrlWordRelay := "h7c".U
+  } .elsewhen( io.downCtrlWordIsK28_4 ){
+    downCtrlWordRelay := "h9c".U
+  } .elsewhen( io.downCtrlWordIsK28_1 ){
+    downCtrlWordRelay := "h3c".U
+  } .elsewhen( io.downCtrlWordIsK28_2 ){
+    downCtrlWordRelay := "h5c".U
+  } .elsewhen( io.downCtrlWordIsK28_6 ){
+    downCtrlWordRelay := "hdc".U
+  }
+
+  when( ~RegNext(isAckProbe,false.B) & isAckProbe ){
+    upCtrlWordRelay := downCtrlWordRelay
+  } .elsewhen( io.upCtrlWordIsK28_0 ) {
+    upCtrlWordRelay := "h1c".U
+  } .elsewhen( io.upCtrlWordIsK28_3 ) {
+    upCtrlWordRelay := "h7c".U
+  } .elsewhen( io.upCtrlWordIsK28_4 ) {
+    upCtrlWordRelay := "h9c".U
+  } .elsewhen( io.upCtrlWordIsK28_1 ) {
+    upCtrlWordRelay := "h3c".U
+  } .elsewhen( io.upCtrlWordIsK28_2 ) {
+    upCtrlWordRelay := "h5c".U
+  } .elsewhen( io.upCtrlWordIsK28_6 ) {
+    upCtrlWordRelay := "hdc".U
+  }
+
+
+}
+
 class SlaveParser extends SlaveParserBase
 with SlaveParserIndex
 with SlaveParserRW