实现同步sync信号的产生，编译未过

src/main/scala/backBoard/shin/Interface.scala

@@ -34,6 +34,8 @@ class CommonRegisterBundle extends Bundle{
   val timeStamp = UInt(64.W)
   val mstDeltaTime = UInt(32.W)
 
+  val syncPoint = UInt(64.W)
+  val syncPeroid = UInt(32.W)
   // val linkStatus = UInt(8.W)
 
 
@@ -92,6 +94,43 @@ class SlaveRegisterBundle extends Bundle{
 
   // val dcSyncEnable = Bool()
   // val dcSyncWidth  = UInt(16.W)
+
+
+
+
+
+
+  // val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
+  // val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
+  // val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
+
+  // val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
+  // val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
+
+
+  // val mstTimeStamp  = UInt(64.W) //主站时间戳
+  val slvDeltaTime  = UInt(32.W) //从站时间戳差值
+  val deltaFinal    = UInt(32.W) //当前时间戳与主站时间差
+  val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
+
+  val syncCfg = UInt(8.W)
+  val syncWidth = Vec(4, UInt(16.W) )
+
+
+
+  val syncOffset = Vec(4, UInt(32.W))
+
+
+
+
+
+
+  // recoTimeStamp = io.timeStamp + deltaFinal
+  // recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp         + deltaMstSlvDeltaTimeStamp
+  // recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - slvDeltaTimeStamp            ) >> 1
+  // recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - (upTimeStamp - downTimeStamp)) >> 1
+
+
 }
 
 
@@ -99,8 +138,9 @@ class SlaveRegisterBundle extends Bundle{
 class InterfaceIO extends Bundle{
   val ospi = new SSPIInterfaceIO
   val oqspi = new QSPIInterfaceIO
-  val iqspi = new QSPIInterfaceIO
+  val iqspi = Flipped(new QSPIInterfaceIO)
 
+  val lvds  = new RegAccessInterfaceIO
 
 
 
@@ -121,12 +161,17 @@ class InterfaceIO extends Bundle{
 
   val cReg = Output(new CommonRegisterBundle)
   val mReg = Output(new MasterRegisterBundle)
-  // val sReg = Output(new SlaveRegisterBundle)
+  val sReg = Output(new SlaveRegisterBundle)
 
 
   // val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
   // val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
-  val mstDeltaTimeStamp = Input(UInt(32.W))
+  // val mstTimeStamp  = Input(UInt(64.W)) //主站时间戳
+  val slvDeltaTime  = Input(UInt(32.W)) //从站时间戳差值
+  val mstDeltaTime  = Input(UInt(32.W))
+  val deltaFinal = Input(UInt(32.W))
+
+  val sync = Output(Vec(4, Bool()))
 }
 
 
@@ -143,7 +188,23 @@ abstract class InterfaceBase extends Module{
 
   val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
   val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
-  // val sReg = Wire(new SlaveRegisterBundle)
+  val sReg = Wire(new SlaveRegisterBundle)
+
+  val syncCfg = RegInit(0.U(8.W)); sReg.syncCfg := syncCfg
+
+  val syncWidth = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) }
+  for( i <- 0 until 4 ) {
+    sReg.syncWidth(i) := syncWidth(i)
+  }
+
+  val syncPoint   = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
+  val syncPeroid  = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
+
+  val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
+  for( i <- 0 until 4 ) {
+    sReg.syncOffset(i) := syncOffset(i)
+  }
+
 
 
 
@@ -183,19 +244,90 @@ abstract class InterfaceBase extends Module{
       }) ++
 
       Seq(
-        (addr === "h1c0".U )  -> cReg.timeStamp(7,0),
-        (addr === "h1c1".U )  -> cReg.timeStamp(15,8),
-        (addr === "h1c2".U )  -> cReg.timeStamp(23,16),
-        (addr === "h1c3".U )  -> cReg.timeStamp(31,24),
-        (addr === "h1c4".U )  -> cReg.timeStamp(39,32),
-        (addr === "h1c5".U )  -> cReg.timeStamp(47,40),
-        (addr === "h1c6".U )  -> cReg.timeStamp(55,48),
-        (addr === "h1c7".U )  -> cReg.timeStamp(63,56),
+        //本地时钟
+        (addr === "h100".U )  -> cReg.timeStamp(7,0),
+        (addr === "h101".U )  -> cReg.timeStamp(15,8),
+        (addr === "h102".U )  -> cReg.timeStamp(23,16),
+        (addr === "h103".U )  -> cReg.timeStamp(31,24),
+        (addr === "h104".U )  -> cReg.timeStamp(39,32),
+        (addr === "h105".U )  -> cReg.timeStamp(47,40),
+        (addr === "h106".U )  -> cReg.timeStamp(55,48),
+        (addr === "h107".U )  -> cReg.timeStamp(63,56),
 
-        (addr === "h1D0".U )  -> io.mstDeltaTimeStamp(7,0),  
-        (addr === "h1D1".U )  -> io.mstDeltaTimeStamp(15,8), 
-        (addr === "h1D2".U )  -> io.mstDeltaTimeStamp(23,16),
-        (addr === "h1D3".U )  -> io.mstDeltaTimeStamp(31,24),
+        //参考主站时钟
+        (addr === "h108".U & isSlvMode)  -> sReg.deltaFinal(7,0),
+        (addr === "h109".U & isSlvMode)  -> sReg.deltaFinal(15,8),
+        (addr === "h10a".U & isSlvMode)  -> sReg.deltaFinal(23,16),
+        (addr === "h10b".U & isSlvMode)  -> sReg.deltaFinal(31,24),
+        // (addr === "h10c".U & isSlvMode)  -> sReg.deltaFinal(39,32),
+        // (addr === "h10d".U & isSlvMode)  -> sReg.deltaFinal(47,40),
+        // (addr === "h10e".U & isSlvMode)  -> sReg.deltaFinal(55,48),
+        // (addr === "h10f".U & isSlvMode)  -> sReg.deltaFinal(63,56),
+
+        //主站发送接收时间差
+        (addr === "h110".U )  -> cReg.mstDeltaTime(7,0),  
+        (addr === "h111".U )  -> cReg.mstDeltaTime(15,8), 
+        (addr === "h112".U )  -> cReg.mstDeltaTime(23,16),
+        (addr === "h113".U )  -> cReg.mstDeltaTime(31,24),
+
+        //从站发送接收时间差
+        (addr === "h114".U & isSlvMode)  -> sReg.slvDeltaTime(7,0),  
+        (addr === "h115".U & isSlvMode)  -> sReg.slvDeltaTime(15,8), 
+        (addr === "h116".U & isSlvMode)  -> sReg.slvDeltaTime(23,16),
+        (addr === "h117".U & isSlvMode)  -> sReg.slvDeltaTime(31,24),
+
+        //校准后的时钟
+        (addr === "h118".U & isSlvMode)  -> sReg.recoTimeStamp(7,0),
+        (addr === "h119".U & isSlvMode)  -> sReg.recoTimeStamp(15,8),
+        (addr === "h11a".U & isSlvMode)  -> sReg.recoTimeStamp(23,16),
+        (addr === "h11b".U & isSlvMode)  -> sReg.recoTimeStamp(31,24),
+        (addr === "h11c".U & isSlvMode)  -> sReg.recoTimeStamp(39,32),
+        (addr === "h11d".U & isSlvMode)  -> sReg.recoTimeStamp(47,40),
+        (addr === "h11e".U & isSlvMode)  -> sReg.recoTimeStamp(55,48),
+        (addr === "h11f".U & isSlvMode)  -> sReg.recoTimeStamp(63,56),
+
+        (addr === "h120".U & isSlvMode)  -> sReg.syncCfg,
+
+        (addr === "h122".U & isSlvMode)  -> sReg.syncWidth(0)(7,0),
+        (addr === "h123".U & isSlvMode)  -> sReg.syncWidth(0)(15,8),
+
+        (addr === "h124".U & isSlvMode)  -> sReg.syncWidth(1)(7,0),
+        (addr === "h125".U & isSlvMode)  -> sReg.syncWidth(1)(15,8),
+
+        (addr === "h126".U & isSlvMode)  -> sReg.syncWidth(2)(7,0),
+        (addr === "h127".U & isSlvMode)  -> sReg.syncWidth(2)(15,8),
+
+        (addr === "h128".U & isSlvMode)  -> sReg.syncWidth(3)(7,0),
+        (addr === "h129".U & isSlvMode)  -> sReg.syncWidth(3)(15,8),
+
+        (addr === "h130".U )  -> cReg.syncPoint(7,0),
+        (addr === "h131".U )  -> cReg.syncPoint(15,8),
+        (addr === "h132".U )  -> cReg.syncPoint(23,16),
+        (addr === "h133".U )  -> cReg.syncPoint(31,24),
+        (addr === "h134".U )  -> cReg.syncPoint(39,32),
+        (addr === "h135".U )  -> cReg.syncPoint(47,40),
+        (addr === "h136".U )  -> cReg.syncPoint(55,48),
+        (addr === "h137".U )  -> cReg.syncPoint(63,56),
+
+        (addr === "h138".U )  -> cReg.syncPeroid(7,0),
+        (addr === "h139".U )  -> cReg.syncPeroid(15,8),
+        (addr === "h13a".U )  -> cReg.syncPeroid(23,16),
+        (addr === "h13b".U )  -> cReg.syncPeroid(31,24),
+
+        (addr === "h13c".U & isSlvMode)  -> sReg.syncOffset(1)(7,0),
+        (addr === "h13d".U & isSlvMode)  -> sReg.syncOffset(1)(15,8),
+        (addr === "h13e".U & isSlvMode)  -> sReg.syncOffset(1)(23,16),
+        (addr === "h13f".U & isSlvMode)  -> sReg.syncOffset(1)(31,24),
+
+        (addr === "h140".U & isSlvMode)  -> sReg.syncOffset(2)(7,0),
+        (addr === "h141".U & isSlvMode)  -> sReg.syncOffset(2)(15,8),
+        (addr === "h142".U & isSlvMode)  -> sReg.syncOffset(2)(23,16),
+        (addr === "h143".U & isSlvMode)  -> sReg.syncOffset(2)(31,24),
+
+        (addr === "h144".U & isSlvMode)  -> sReg.syncOffset(3)(7,0),
+        (addr === "h145".U & isSlvMode)  -> sReg.syncOffset(3)(15,8),
+        (addr === "h146".U & isSlvMode)  -> sReg.syncOffset(3)(23,16),
+        (addr === "h147".U & isSlvMode)  -> sReg.syncOffset(3)(31,24),
       )
 
     )
@@ -203,7 +335,12 @@ abstract class InterfaceBase extends Module{
 
 
 
-
+  //spi信号
+  val addrSel = Wire(UInt(16.W))
+  val dataw   = Wire( UInt(8.W) )
+  val datar   = Wire( UInt(8.W) )  
+  val isEnW = Wire(Bool())
+  val isEnR = Wire(Bool())
 
 
 }
@@ -216,32 +353,32 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
 
 
-  val isEnW = Mux1H(Seq(
+  isEnW := Mux1H(Seq(
     ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnW,
     ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnW,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW,
   ))
     
-  val addrSel = Mux1H(Seq(
+  addrSel := Mux1H(Seq(
     ( cReg.spiSel === 0.U ) -> iQSpi.io.addrSel,
     ( cReg.spiSel === 1.U ) ->  oSpi.io.addrSel,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.addrSel,
   ))
 
-  val dataw = Mux1H(Seq(
+  dataw := Mux1H(Seq(
     ( cReg.spiSel === 0.U ) -> iQSpi.io.dataw,
     ( cReg.spiSel === 1.U ) ->  oSpi.io.dataw,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.dataw,
   ))
 
-  val isEnR = Mux1H(Seq(
+  isEnR := Mux1H(Seq(
     ( cReg.spiSel === 0.U ) -> iQSpi.io.isEnR,
     ( cReg.spiSel === 1.U ) ->  oSpi.io.isEnR,
     ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnR,
   ))
 
-  val datar = MuxCase( 0.U, Array(
-      ((addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
+  datar := MuxCase( 0.U, Array(
+      ((addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrSel), 0.U, isEnR ),
       ((addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
       ((addrSel & "hFF00".U) === "h1000".U) -> 0.U,
       ((addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
@@ -303,10 +440,59 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     )
 
 
+  when( isEnW & isSlvMode ){
+    when( addrSel === "h120".U ){
+      syncCfg := dataw
+    }
 
+    for( i <- 0 until 4 ){
+      when( io.lvds.addrSel === ("h122".U + (2*i).U)){
+        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
+      } .elsewhen( io.lvds.addrSel === ("h123".U + (2*i).U) ){
+        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
+      }
+    }
 
+    when( addrSel === "h130".U ){
+      syncPoint := Cat( syncPoint(63,8), dataw ) 
+    } .elsewhen( addrSel === "h131".U ){
+      syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) ) 
+    } .elsewhen( addrSel === "h132".U ){
+      syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) ) 
+    } .elsewhen( addrSel === "h133".U ){
+      syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) ) 
+    } .elsewhen( addrSel === "h134".U ){
+      syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) ) 
+    } .elsewhen( addrSel === "h135".U ){
+      syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) ) 
+    } .elsewhen( addrSel === "h136".U ){
+      syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) ) 
+    } .elsewhen( addrSel === "h137".U ){
+      syncPoint := Cat( dataw, syncPoint(55,0) ) 
+    }
 
+    .elsewhen( addrSel === "h138".U ){
+      syncPeroid := Cat( syncPeroid(31,8), dataw ) 
+    } .elsewhen( addrSel === "h139".U ){
+      syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) ) 
+    } .elsewhen( addrSel === "h13a".U ){
+      syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) ) 
+    } .elsewhen( addrSel === "h13b".U ){
+      syncPeroid := Cat( dataw, syncPeroid(23,0) ) 
+    }
 
+    for( i <- 1 until 4 ){
+      when( addrSel === ("h13c".U + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,8), dataw ) 
+      } .elsewhen( addrSel === ("h13d".U + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) ) 
+      } .elsewhen( addrSel === ("h13e".U + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) ) 
+      } .elsewhen( addrSel === ("h13f".U + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) ) 
+      }      
+    }
+  }
 
 
 
@@ -370,18 +556,132 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
 
 trait InterfaceLVDSop{ this: InterfaceBase =>
   
+  // io.lvds.addrSel = Output(UInt(16.W))
+  // io.lvds.dataw   = Output( UInt(8.W) )
+  // io.lvds.datar   = Input( UInt(8.W) )
+  // io.lvds.isEnW   = Output(Bool())
+  // io.lvds.isEnR   = Output(Bool())
+
+  io.lvds.datar = RegEnable( AcquireReg(addr = io.lvds.addrSel), 0.U, io.lvds.isEnR )
+
+  when( io.lvds.isEnW & isSlvMode ){
+
+    when( io.lvds.addrSel === "h120".U ){
+      syncCfg := io.lvds.dataw
+    }
+
+    for( i <- 0 until 4 ){
+      when( io.lvds.addrSel === ("h122".U + (2*i).U)){
+        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
+      } .elsewhen( io.lvds.addrSel === ("h123".U + (2*i).U) ){
+        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
+      }
+    }
+
+    .elsewhen( io.lvds.addrSel === "h130".U ){
+      syncPoint := Cat( syncPoint(63,8), io.lvds.dataw ) 
+    } .elsewhen( io.lvds.addrSel === "h131".U ){
+      syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) ) 
+    } .elsewhen( io.lvds.addrSel === "h132".U ){
+      syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) ) 
+    } .elsewhen( io.lvds.addrSel === "h133".U ){
+      syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) ) 
+    } .elsewhen( io.lvds.addrSel === "h134".U ){
+      syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) ) 
+    } .elsewhen( io.lvds.addrSel === "h135".U ){
+      syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) ) 
+    } .elsewhen( io.lvds.addrSel === "h136".U ){
+      syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) ) 
+    } .elsewhen( io.lvds.addrSel === "h137".U ){
+      syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) ) 
+    }
+
+    .elsewhen( io.lvds.addrSel === "h138".U ){
+      syncPeroid := Cat( syncPeroid(31,8), io.lvds.dataw ) 
+    } .elsewhen( io.lvds.addrSel === "h139".U ){
+      syncPeroid := Cat( syncPeroid(31,16), io.lvds.dataw, syncPeroid(7,0) ) 
+    } .elsewhen( io.lvds.addrSel === "h13a".U ){
+      syncPeroid := Cat( syncPeroid(31,24), io.lvds.dataw, syncPeroid(15,0) ) 
+    } .elsewhen( io.lvds.addrSel === "h13b".U ){
+      syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) ) 
+    }
+
+    for( i <- 1 until 4 ){
+      when( io.lvds.addrSel === ("h13c".U + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw ) 
+      } .elsewhen( io.lvds.addrSel === ("h13d".U + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,16), io.lvds.dataw, syncOffset(i)(7,0) ) 
+      } .elsewhen( io.lvds.addrSel === ("h13e".U + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( syncOffset(i)(31,24), io.lvds.dataw, syncOffset(i)(15,0) ) 
+      } .elsewhen( io.lvds.addrSel === ("h13f".U + (4*(i-1)).U) ){
+        syncOffset(i) := Cat( io.lvds.dataw, syncOffset(i)(23,0) ) 
+      }      
+    }
+  }
 }
 
 trait InterfaceSync{ this: InterfaceBase =>
   cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
 
-  cReg.mstDeltaTime := io.mstDeltaTimeStamp
+  cReg.mstDeltaTime := io.mstDeltaTime
     // Cat(
       //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d3".U ),
       //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d2".U ),
       //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d1".U ),
       //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d0".U ),
     // )
+
+  // sReg.mstTimeStamp := io.mstTimeStamp
+  sReg.deltaFinal := io.deltaFinal
+  sReg.recoTimeStamp := RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
+  sReg.slvDeltaTime := io.slvDeltaTime
+  
+  val syncSign = for( i <- 0 until 4 ) yield { RegInit(false.B) }
+  val syncOffsetCnt = for( i <- 0 until 4 ) yield { RegInit("hFFFFFFFF".U(32.W)) } //空开第0位
+  val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
+
+
+  when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
+    syncSign(0) := true.B
+    cReg.syncPoint := cReg.syncPoint + cReg.syncPeroid
+  } .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){
+    syncSign(0) := false.B
+  } .elsewhen( sReg.syncCfg(4+0) & isEnW & addrSel === "h122".U ){
+    syncSign(0) := false.B
+  }
+
+  for( i <- 1 until 4 ) {
+
+    when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
+      syncOffsetCnt(i) := 0.U
+    } .elsewhen( syncOffsetCnt(i) < sReg.syncOffset(i) ){
+      syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
+    }
+
+    when( syncOffsetCnt(i) === sReg.syncOffset(i) ){
+      syncSign(i) := true.B
+    } .elsewhen( ~sReg.syncCfg(4+i) & syncResetCnt(i) === sReg.syncWidth(i) ){
+      syncSign(i) := false.B
+    } .elsewhen( sReg.syncCfg(4+i) & isEnW & addrSel === ("h122".U + (2*i).U) ){
+      syncSign(i) := false.B
+    }
+
+  }
+
+  for( i <- 0 until 4 ){
+    when( ~sReg.syncCfg(4+i) & syncSign(i) ){
+      syncResetCnt(i) := syncResetCnt(i) + 1.U
+    }
+  }
+
+
+
+
+  io.sync(0) := sReg.syncCfg.extract(0) & syncSign(0) & isSlvMode
+  io.sync(1) := sReg.syncCfg.extract(1) & syncSign(1) & isSlvMode
+  io.sync(2) := sReg.syncCfg.extract(2) & syncSign(2) & isSlvMode
+  io.sync(3) := sReg.syncCfg.extract(3) & syncSign(3) & isSlvMode
+
 }
 
 class Interface extends InterfaceBase
@@ -401,4 +701,9 @@ with InterfaceSync
   // io.smDeqAddr := cReg.smDeqAddr
 
 
+
+
+
+
+
 }

src/main/scala/backBoard/shin/ShinTop.scala

@@ -40,10 +40,16 @@ class ShinTopIO extends Bundle{
     val isError = Bool()
     val length  = UInt(12.W)
   })
+
+  val iSync = Output(Vec(4, Bool()))
+  val oSync = Output(Vec(4, Bool()))
 }
 
 
 
+
+
+
 abstract class ShinTopBase extends Module{
   val io: ShinTopIO = IO(new ShinTopIO)
 
@@ -79,6 +85,9 @@ abstract class ShinTopBase extends Module{
   io.iqspi <> interface.io.iqspi
   io.oqspi <> interface.io.oqspi
 
+  io.iSync := interface.io.sync
+  io.oSync := interface.io.sync
+
   val sram = Seq(
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
@@ -210,7 +219,11 @@ abstract class ShinTopBase extends Module{
     upCDROut.io.axis.valid := false.B
     upCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
 
-    interface.io.mstDeltaTimeStamp := 0.U
+    interface.io.mstDeltaTime := 0.U
+
+    interface.io.slvDeltaTime := 0.U
+    interface.io.deltaFinal   := 0.U
+
 
   }
 
@@ -265,7 +278,7 @@ trait ShinTopMaster{ this: ShinTopBase =>
     // _ := interface.io.smDeqAddr(7)
 
 
-    interface.io.mstDeltaTimeStamp := masterParser.io.deltaTimeStamp
+    interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp
   }
 
   masterParser.io.req.valid         := interface.io.txReq.valid
@@ -327,11 +340,12 @@ trait ShinTopSlave{ this: ShinTopBase =>
     smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
     smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
 
-    interface.io.mstDeltaTimeStamp := slaveParser.io.mstDeltaTimeStamp
-
+    interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp
+    interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime
+    interface.io.deltaFinal   := slaveParser.io.deltaFinal
   }
 
-
+  interface.io.lvds <> slaveParser.io.lvds
 }
 
 

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -47,9 +47,14 @@ class SlaveParserIO extends Bundle{
   val trigAddr = Input( Vec(8, UInt(15.W)) )
 
   val mstDeltaTimeStamp = Output(UInt(32.W))
+  val slvDeltaTimeStamp = Output(UInt(32.W))
+  val deltaFinal        = Output(UInt(32.W))
+
   val isLoop = Output(Bool())
 
   val cReg = Input(new CommonRegisterBundle)
+
+  val lvds  = new RegAccessInterfaceIO
 }
 
 abstract class SlaveParserBase extends Module{
@@ -387,7 +392,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   val addrw = Reg(UInt(15.W))
 
-  val isWRRegister = (addrw(14,11) === "b0000".U)
+  val isWRReg = (addrw(14,11) === "b0000".U)
   val isWRSM0      = (addrw(14,11) === "b0001".U)
   val isWRSM2      = (addrw(14,11) === "b0011".U)
   val isWRSM4      = (addrw(14,11) === "b0101".U)
@@ -406,8 +411,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   }
 
 
-
-
+  io.lvds.isEnW   := isWrite & isWRReg
+  io.lvds.dataw   := downRecParser.io.data.bits
 
   io.sram_w(0).enw   := isWrite & isWRSM0
   io.sram_w(0).addrw := addrw(10,0)
@@ -467,7 +472,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA    ) -> addrr,
   ))
 
-  val isRDRegister = (readSMAddr(14,11) === "b0000".U)
+  val isRDReg      = (readSMAddr(14,11) === "b0000".U)
   val isRDSM1      = (readSMAddr(14,11) === "b0010".U)
   val isRDSM3      = (readSMAddr(14,11) === "b0100".U)
   val isRDSM5      = (readSMAddr(14,11) === "b0110".U)
@@ -480,7 +485,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   }
 
   val upStreamData = Mux1H(Seq(
-    isRDRegister -> 0.U,
+    isRDReg      -> io.lvds.datar,
     isRDSM1      -> io.sram_r(0).datar,
     isRDSM3      -> io.sram_r(1).datar,
     isRDSM5      -> io.sram_r(2).datar,
@@ -508,6 +513,16 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   }
 
+  io.lvds.isEnR   := isRead & isRDReg
+  io.lvds.addrSel := Mux1H(Seq(
+    isRead  -> readSMAddr(10,0)
+    isWrite -> addrw(10,0)
+  ))
+  assert( ~(isRead & isWrite) )
+  
+
+
+
   io.sram_r(0).enr := isRead & isRDSM1
   io.sram_r(1).enr := isRead & isRDSM3
   io.sram_r(2).enr := isRead & isRDSM5
@@ -537,17 +552,16 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
   val mstTimeStamp  = Reg(UInt(64.W)) //主站时间戳
   val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
-  val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值
+  val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTime //从站时间戳差值
 
   val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
   val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
-  val deltaFinal = Reg(UInt(32.W)) //当前时间戳与主站时间差
+  val deltaFinal = Reg(UInt(32.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
 
 
-  val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
+  // val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
 
-  dontTouch(deltaFinal)
-  dontTouch(recoTimeStamp)
+  // dontTouch(recoTimeStamp)
 
   // recoTimeStamp = io.timeStamp + deltaFinal
   // recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp         + deltaMstSlvDeltaTimeStamp

src/main/scala/backBoard/shin/SpiInterface.scala

@@ -19,15 +19,16 @@ class SSPIInterfaceIO extends Bundle{
   val csn  = Input(Bool())
 }
 
+class RegAccessInterfaceIO extends Bundle{
+  val addrSel = Output(UInt(16.W))
+  val dataw   = Output( UInt(8.W) )
+  val datar   = Input( UInt(8.W) )
+  val isEnW   = Output(Bool())
+  val isEnR   = Output(Bool())
+}
 
 abstract class SpiInterfaceBase extends Module{
-  val io = IO(new Bundle{
-    val addrSel = Output(UInt(16.W))
-    val dataw   = Output( UInt(8.W) )
-    val datar   = Input( UInt(8.W) )
-    val isEnW   = Output(Bool())
-    val isEnR   = Output(Bool())
-  })
+  val io = IO(new RegAccessInterfaceIO)
 
   val sck     = Wire(Bool())
   val csn     = Wire(Bool())