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实现同步sync信号的产生，编译未过

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This commit is contained in:
Ruige Lee
2025-05-15 18:40:01 +08:00
parent f71b8553cb
commit f20efe5b25
4 changed files with 380 additions and 46 deletions
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15
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -19,15 +19,16 @@ class SSPIInterfaceIO extends Bundle{
val csn = Input(Bool())
}
class RegAccessInterfaceIO extends Bundle{
val addrSel = Output(UInt(16.W))
val dataw = Output( UInt(8.W) )
val datar = Input( UInt(8.W) )
val isEnW = Output(Bool())
val isEnR = Output(Bool())
}
abstract class SpiInterfaceBase extends Module{
val io = IO(new Bundle{
val addrSel = Output(UInt(16.W))
val dataw = Output( UInt(8.W) )
val datar = Input( UInt(8.W) )
val isEnW = Output(Bool())
val isEnR = Output(Bool())
})
val io = IO(new RegAccessInterfaceIO)
val sck = Wire(Bool())
val csn = Wire(Bool())