实现同步sync信号的产生，编译未过

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -47,9 +47,14 @@ class SlaveParserIO extends Bundle{
   val trigAddr = Input( Vec(8, UInt(15.W)) )
 
   val mstDeltaTimeStamp = Output(UInt(32.W))
+  val slvDeltaTimeStamp = Output(UInt(32.W))
+  val deltaFinal        = Output(UInt(32.W))
+
   val isLoop = Output(Bool())
 
   val cReg = Input(new CommonRegisterBundle)
+
+  val lvds  = new RegAccessInterfaceIO
 }
 
 abstract class SlaveParserBase extends Module{
@@ -387,7 +392,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   val addrw = Reg(UInt(15.W))
 
-  val isWRRegister = (addrw(14,11) === "b0000".U)
+  val isWRReg = (addrw(14,11) === "b0000".U)
   val isWRSM0      = (addrw(14,11) === "b0001".U)
   val isWRSM2      = (addrw(14,11) === "b0011".U)
   val isWRSM4      = (addrw(14,11) === "b0101".U)
@@ -406,8 +411,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   }
 
 
-
-
+  io.lvds.isEnW   := isWrite & isWRReg
+  io.lvds.dataw   := downRecParser.io.data.bits
 
   io.sram_w(0).enw   := isWrite & isWRSM0
   io.sram_w(0).addrw := addrw(10,0)
@@ -467,7 +472,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA    ) -> addrr,
   ))
 
-  val isRDRegister = (readSMAddr(14,11) === "b0000".U)
+  val isRDReg      = (readSMAddr(14,11) === "b0000".U)
   val isRDSM1      = (readSMAddr(14,11) === "b0010".U)
   val isRDSM3      = (readSMAddr(14,11) === "b0100".U)
   val isRDSM5      = (readSMAddr(14,11) === "b0110".U)
@@ -480,7 +485,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   }
 
   val upStreamData = Mux1H(Seq(
-    isRDRegister -> 0.U,
+    isRDReg      -> io.lvds.datar,
     isRDSM1      -> io.sram_r(0).datar,
     isRDSM3      -> io.sram_r(1).datar,
     isRDSM5      -> io.sram_r(2).datar,
@@ -508,6 +513,16 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   }
 
+  io.lvds.isEnR   := isRead & isRDReg
+  io.lvds.addrSel := Mux1H(Seq(
+    isRead  -> readSMAddr(10,0)
+    isWrite -> addrw(10,0)
+  ))
+  assert( ~(isRead & isWrite) )
+  
+
+
+
   io.sram_r(0).enr := isRead & isRDSM1
   io.sram_r(1).enr := isRead & isRDSM3
   io.sram_r(2).enr := isRead & isRDSM5
@@ -537,17 +552,16 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
   val mstTimeStamp  = Reg(UInt(64.W)) //主站时间戳
   val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
-  val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值
+  val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTime //从站时间戳差值
 
   val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
   val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
-  val deltaFinal = Reg(UInt(32.W)) //当前时间戳与主站时间差
+  val deltaFinal = Reg(UInt(32.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
 
 
-  val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
+  // val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
 
-  dontTouch(deltaFinal)
-  dontTouch(recoTimeStamp)
+  // dontTouch(recoTimeStamp)
 
   // recoTimeStamp = io.timeStamp + deltaFinal
   // recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp         + deltaMstSlvDeltaTimeStamp