实现同步sync信号的产生，编译未过

src/main/scala/backBoard/shin/ShinTop.scala

@@ -40,10 +40,16 @@ class ShinTopIO extends Bundle{
     val isError = Bool()
     val length  = UInt(12.W)
   })
+
+  val iSync = Output(Vec(4, Bool()))
+  val oSync = Output(Vec(4, Bool()))
 }
 
 
 
+
+
+
 abstract class ShinTopBase extends Module{
   val io: ShinTopIO = IO(new ShinTopIO)
 
@@ -79,6 +85,9 @@ abstract class ShinTopBase extends Module{
   io.iqspi <> interface.io.iqspi
   io.oqspi <> interface.io.oqspi
 
+  io.iSync := interface.io.sync
+  io.oSync := interface.io.sync
+
   val sram = Seq(
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
@@ -210,7 +219,11 @@ abstract class ShinTopBase extends Module{
     upCDROut.io.axis.valid := false.B
     upCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
 
-    interface.io.mstDeltaTimeStamp := 0.U
+    interface.io.mstDeltaTime := 0.U
+
+    interface.io.slvDeltaTime := 0.U
+    interface.io.deltaFinal   := 0.U
+
 
   }
 
@@ -265,7 +278,7 @@ trait ShinTopMaster{ this: ShinTopBase =>
     // _ := interface.io.smDeqAddr(7)
 
 
-    interface.io.mstDeltaTimeStamp := masterParser.io.deltaTimeStamp
+    interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp
   }
 
   masterParser.io.req.valid         := interface.io.txReq.valid
@@ -327,11 +340,12 @@ trait ShinTopSlave{ this: ShinTopBase =>
     smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
     smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
 
-    interface.io.mstDeltaTimeStamp := slaveParser.io.mstDeltaTimeStamp
-
+    interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp
+    interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime
+    interface.io.deltaFinal   := slaveParser.io.deltaFinal
   }
 
-
+  interface.io.lvds <> slaveParser.io.lvds
 }