From f12bc41c527cbcb6a451647e42ae874696804771 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 15 Jan 2025 11:23:02 +0800
Subject: [PATCH] tl2cdr api

---
 tb/sw/tl2cdr/tl2cdr.c | 111 ++++++++++++++++++++++++++++++++++++++++++
 tb/sw/tl2cdr/tl2cdr.h |  32 ++++++++++++
 2 files changed, 143 insertions(+)
 create mode 100644 tb/sw/tl2cdr/tl2cdr.c
 create mode 100644 tb/sw/tl2cdr/tl2cdr.h

diff --git a/tb/sw/tl2cdr/tl2cdr.c b/tb/sw/tl2cdr/tl2cdr.c
new file mode 100644
index 0000000..adc79fc
--- /dev/null
+++ b/tb/sw/tl2cdr/tl2cdr.c
@@ -0,0 +1,111 @@
+#include <stdint.h>
+#include "tl2cdr.h"
+
+#ifndef TL2CDR_BASE
+#error TL2CDR Base address not define!!!
+#endif
+
+volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
+volatile uint32_t *cdr_txLen  = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
+volatile uint32_t *cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
+volatile uint32_t *cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
+
+volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
+volatile uint32_t *cdr_rxLen     = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
+volatile uint32_t *cdr_rxFifo    = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
+
+void cdr_set_downStream(){
+	*cdr_softReset = 1; //复位脉冲
+	*cdr_direct = 0;
+}
+
+void cdr_set_upStream(){
+	*cdr_softReset = 1; //复位脉冲
+	*cdr_direct = 1;
+}
+
+
+void cdr_simple_tx( uint32_t txLen, uint8_t operator, uint8_t* data){
+	//发送下行包头
+	assert(txLen < 2^12);
+	assert(txLen > 8 );
+	assert(txLen % 4 == 0 );
+	assert(operator < 2^4);
+
+	*cdr_txLen = txLen;
+	*cdr_txFifo = (uint32_t)( txLen << 20) | ( operator << 16) | 0x0000;
+	*cdr_txFifo = (uint32_t)0x00;
+
+	for( uint32_t i = 0; i < (txLen-8)/4; i ++ ){
+		*cdr_txFifo = data[4*i+3]<< 24 | data[4*i+2]<<16 | data[4*i+1]<< 8 | data[4*i+0] << 0;
+	}
+
+
+
+}
+
+
+uint32_t cdr_wait_tx_finish(){
+	// //等待发送完成标志
+	// asm volatile (
+	// 	"1:\n"
+	// 	"andi %0, sp, 0x01\n"
+	// 	"beqz %0, 1b\n"
+	// 	"andi sp, sp, 0xFE\n"
+	// 	:"+r"(flag)
+	// );	
+}
+
+uint32_t cdr_wait_rx_start(){
+	//接收第一个包
+	asm volatile (
+		"1:\n"
+		"andi %0, sp, 0x04\n"
+		"beqz %0, 1b\n"
+		"andi sp, sp, 0xFB\n"
+		:"+r"(flag)
+	);	
+}
+
+uint32_t cdr_check_rx_fail(){
+
+}
+
+void cdr_simple_rx(uint32_t* rxLen, uint8_t* operator, uint8_t* data){
+	
+
+	uint32_t readDat;
+
+	readDat = *cdr_rxFifo;	
+
+	&operator = (readDat >> 16) & 0xf;
+	&rxLen    = readDat >> 20;
+
+	readDat = *cdr_rxFifo;
+
+
+	for( uint32_t i = 0; i < (&rxLen >> 2); i ++ ){ //一次传4byte
+		readDat = *cdr_rxFifo;
+		data[4*i+1] = (uint8_t)( (readDat >>  0) & 0xFF);
+		data[4*i+0] = (uint8_t)( (readDat >>  8) & 0xFF);
+		data[4*i+2] = (uint8_t)( (readDat >> 16) & 0xFF);
+		data[4*i+3] = (uint8_t)( (readDat >> 24) & 0xFF);
+	}
+
+	//CRC
+	uint32_t crc = *cdr_rxFifo; //CRC
+
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/tb/sw/tl2cdr/tl2cdr.h b/tb/sw/tl2cdr/tl2cdr.h
new file mode 100644
index 0000000..af2b26c
--- /dev/null
+++ b/tb/sw/tl2cdr/tl2cdr.h
@@ -0,0 +1,32 @@
+#ifndef _TL2CDR_H_
+#define _TL2CDR_H_
+
+#include <stdint.h>
+
+#define TL2CDR_BASE 0x10000000U
+
+
+// volatile uint32_t *cdr_status = (uint32_t*)( 0x000 + 0x0 ); //read
+// volatile uint32_t *cdr_txLen  = (uint32_t*)( 0x000 + 0x4 ); //write
+// volatile uint32_t *cdr_txFifo = (uint32_t*)( 0x000 + 0x8 ); //write
+// volatile uint32_t *cdr_direct = (uint32_t*)( 0x000 + 0xc ); //write
+
+// volatile uint32_t *cdr_softReset = (uint32_t*)( 0x000 + 0x10 ); //write
+// volatile uint32_t *cdr_rxLen     = (uint32_t*)( 0x000 + 0x18 ); //read
+// volatile uint32_t *cdr_rxFifo    = (uint32_t*)( 0x000 + 0x1c ); //read
+
+#define CDR_ReadStatus     0x00
+#define CDR_WriteTxLen     0x04
+#define CDR_WriteTxFifo    0x08
+#define CDR_WriteTransDir  0x0c
+#define CDR_WriteSoftReset 0x10
+#define CDR_ReadRxLen      0x18
+#define CDR_ReadRxFifo     0x1c
+
+
+// extern uint8_t gpio_read();
+// extern uint32_t gpio_write( uint32_t data );
+
+// void gpio_test();
+
+#endif