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高云FPGA：dout输出反相

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Ruige Lee
2025-03-18 15:46:16 +08:00
parent 3c63a7accc
commit eec4d5c18a
1 changed files with 1 additions and 1 deletions
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src/main/scala/backBoard/Dout16.scala
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@@ -106,7 +106,7 @@ with BackBoardSlvOut16{
upReg(13) := outReg(15,8) upReg(13) := outReg(15,8)
} }
out := outPin out := ~outPin
} }