高云FPGA：dout输出反相

2025-03-18 15:46:16 +08:00
parent 3c63a7accc
commit eec4d5c18a
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/backBoard/Dout16.scala
+++ b/src/main/scala/backBoard/Dout16.scala
@@ -106,7 +106,7 @@ with BackBoardSlvOut16{
    upReg(13) := outReg(15,8)
  }

-  out := outPin
+  out := ~outPin

 }