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QSPI修正可用

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This commit is contained in:
Ruige Lee
2025-05-14 16:26:20 +08:00
parent 2e186a8365
commit ed9bf22016
3 changed files with 113 additions and 133 deletions
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8
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -230,8 +230,12 @@ trait InterfaceMCUop{ this: InterfaceBase =>
oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U) oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U) oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)
when( isEnW ){
printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrSel)
}
when( isEnR ){
printf(s"SPI/QSPI Readout 0x%x, @0x%x\n", datar, addrSel)
}

22
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -57,8 +57,8 @@ abstract class SpiInterfaceBase extends Module{
val byteSel = Reg(UInt(12.W)) val byteSel = Reg(UInt(12.W))
io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & isSpiRead & byteSel >= 3.U io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & isSpiWrite & byteSel >= 3.U io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exReg io.dataw := exReg
when( shiftCSn(2) & ~shiftCSn(1) ){ when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -73,12 +73,12 @@ abstract class SpiInterfaceBase extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrSel := 0.U addrSel := 0.U
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrSel := exReg addrSel := exReg
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrSel := Cat(exReg, addrSel(7,0)) addrSel := Cat(exReg, addrSel(7,0))
} .otherwise{ // byteSel > 1.U } .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 2.U & bitSel.andR ){ when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrSel := addrSel + 1.U addrSel := addrSel + 1.U
} }
} }
@@ -86,7 +86,7 @@ abstract class SpiInterfaceBase extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiCmd := "hFF".U spiCmd := "hFF".U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel.andR ){ //CS为低，且SCK上跳的第0byte } .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := exReg spiCmd := exReg
} }
@@ -113,8 +113,8 @@ class SSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel.andR ){ //CS为低，且SCK上跳补一拍 的第0bit } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
exReg := 0.U exReg := 0.U
} .otherwise{ } .otherwise{
when( isSpiWrite ){ when( isSpiWrite ){
@@ -149,8 +149,8 @@ class QSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel.andR ){ //CS为低，且SCK上跳补一拍 的第0bit } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
exReg := 0.U exReg := 0.U
} .otherwise{ } .otherwise{
when( isSpiWrite ){ when( isSpiWrite ){
@@ -162,7 +162,7 @@ class QSpiInterface extends SpiInterfaceBase{
} }
} }
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(6 ,4), shiftMOSI(1) ) exReg := Cat( exReg(3,0), shiftMOSI(1) )
} }

210
tb/shinTest/ShinTopSpiTb.v
View File

@@ -15,7 +15,11 @@ module ShinTopSpiTb(
wire spi_sck; wire spi_sck;
wire spi_mosi; wire spi_mosi;
wire spi_miso; wire spi_miso;
reg [4:0] spi_csn; reg [14:0] spi_csn;
wire qspi_sck;
wire [3:0] qspi_mosi;
wire [3:0] qspi_miso;
wire isResp; wire isResp;
@@ -29,10 +33,23 @@ ShinTop s_ShinTop_Mst(
.io_uDatIn(uDat_w[0]), .io_uDatIn(uDat_w[0]),
.io_uDatOut(), .io_uDatOut(),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[0]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[0]), .io_ospi_csn (spi_csn[5]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[10]),
.io_rsp_valid(isResp), .io_rsp_valid(isResp),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -49,10 +66,22 @@ ShinTop s_ShinTop_slv0(
.io_uDatIn(uDat_w[1]), .io_uDatIn(uDat_w[1]),
.io_uDatOut(uDat_w[0]), .io_uDatOut(uDat_w[0]),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[1]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[1]), .io_ospi_csn (spi_csn[6]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[11]),
.io_rsp_valid(), .io_rsp_valid(),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -69,10 +98,22 @@ ShinTop s_ShinTop_slv1(
.io_uDatIn(uDat_w[2]), .io_uDatIn(uDat_w[2]),
.io_uDatOut(uDat_w[1]), .io_uDatOut(uDat_w[1]),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[2]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[2]), .io_ospi_csn (spi_csn[7]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[12]),
.io_rsp_valid(), .io_rsp_valid(),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -89,10 +130,22 @@ ShinTop s_ShinTop_slv2(
.io_uDatIn(uDat_w[3]), .io_uDatIn(uDat_w[3]),
.io_uDatOut(uDat_w[2]), .io_uDatOut(uDat_w[2]),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[3]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[3]), .io_ospi_csn (spi_csn[8]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[13]),
.io_rsp_valid(), .io_rsp_valid(),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -109,10 +162,22 @@ ShinTop s_ShinTop_slv3(
.io_uDatIn(1'b0), .io_uDatIn(1'b0),
.io_uDatOut(uDat_w[3]), .io_uDatOut(uDat_w[3]),
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[4]),
.io_ospi_sck (spi_sck), .io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi), .io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso), .io_ospi_miso(spi_miso),
.io_ospi_csn (spi_csn[4]), .io_ospi_csn (spi_csn[9]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[14]),
.io_rsp_valid(), .io_rsp_valid(),
.io_rsp_bits_isError(), .io_rsp_bits_isError(),
@@ -132,7 +197,7 @@ initial begin
clk8x = 0; clk8x = 0;
reset = 0; reset = 0;
spi_csn = 5'b11111; spi_csn = ~15'b0;
#100 #100
reset <= 1; reset <= 1;
@@ -192,23 +257,17 @@ end
end end
assign spi_sck = sck; assign spi_sck = sck;
assign qspi_sck = sck;
reg [7:0] txBuf[0:2047]; reg [7:0] txBuf[0:2047];
reg [7:0] rxBuf[0:2047]; reg [7:0] rxBuf[0:2047];
reg [7:0] exChangeReg; reg [7:0] exChangeReg;
reg [7:0] exChangeReg0;
reg [7:0] exChangeReg1;
reg [7:0] exChangeReg2;
reg [7:0] exChangeReg3;
reg [7:0] exChangeReg4;
// assign spi_mosi[0] = exChangeReg0[7];
// assign spi_mosi[1] = exChangeReg1[7];
// assign spi_mosi[2] = exChangeReg2[7];
// assign spi_mosi[3] = exChangeReg3[7];
// assign spi_mosi[4] = exChangeReg4[7];
assign spi_mosi = exChangeReg[7]; assign spi_mosi = exChangeReg[7];
assign qspi_mosi = exChangeReg[7:4];
reg isReq = 0; reg isReq = 0;
reg isBusy = 0; reg isBusy = 0;
@@ -226,8 +285,8 @@ always @(posedge clock) begin
isBusy <= #5 1'b1; isBusy <= #5 1'b1;
transCnt <= #5 0; transCnt <= #5 0;
byteCnt <= #5 0; byteCnt <= #5 ~12'b0;
bitCnt <= #5 0; bitCnt <= #5 ~3'b0;
spi_csn[idx] <= #5 1'b0; spi_csn[idx] <= #5 1'b0;
exChangeReg <= txBuf[0]; exChangeReg <= txBuf[0];
@@ -235,124 +294,41 @@ always @(posedge clock) begin
end end
wire isQspi = (idx >= 0 && idx <= 4) || idx >= 10;
wire [11:0] nextByteCnt = byteCnt +1;
always @(posedge sck) begin always @(posedge sck) begin
if( isBusy ) begin if( isBusy ) begin
if( transCnt < length ) begin if( transCnt <= length ) begin
if( isQspi ) begin
bitCnt <= ~bitCnt;
end else begin
bitCnt <= bitCnt + 1; bitCnt <= bitCnt + 1;
end
if( bitCnt == 7 ) begin if( &bitCnt ) begin
byteCnt <= byteCnt +1; byteCnt <= byteCnt +1;
transCnt <= transCnt + 1; transCnt <= transCnt + 1;
rxBuf[byteCnt] <= exChangeReg; rxBuf[byteCnt] <= exChangeReg;
exChangeReg <= txBuf[byteCnt+1]; exChangeReg <= txBuf[nextByteCnt];
end else begin
if( isQspi ) begin
exChangeReg <= {exChangeReg[3:0], qspi_miso};
end else begin end else begin
exChangeReg <= {exChangeReg[6:0], spi_miso}; exChangeReg <= {exChangeReg[6:0], spi_miso};
end end
end
end else begin end else begin
isBusy <= #5 1'b0; isBusy <= #5 1'b0;
spi_csn[idx] <= #5 1'b1; spi_csn[idx] <= #5 1'b1;
end end
end end
end end
// task spi_trans( );
// begin
// #10
// `SCKFRE spi_sck[idx] <= 1'b0;
// if( idx == 0 ) exChangeReg0 <= #5 address[7:0];
// else if( idx == 1 ) exChangeReg1 <= #5 address[7:0];
// else if( idx == 2 ) exChangeReg2 <= #5 address[7:0];
// else if( idx == 3 ) exChangeReg3 <= #5 address[7:0];
// else if( idx == 4 ) exChangeReg4 <= #5 address[7:0];
// `SCKFRE spi_sck[idx] <= 1'b1;
// `SCKFRE spi_sck[idx] <= 1'b0;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// if( idx == 0 ) exChangeReg0 <= #5 address[15:8];
// else if( idx == 1 ) exChangeReg1 <= #5 address[15:8];
// else if( idx == 2 ) exChangeReg2 <= #5 address[15:8];
// else if( idx == 3 ) exChangeReg3 <= #5 address[15:8];
// else if( idx == 4 ) exChangeReg4 <= #5 address[15:8];
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// if( idx == 0 ) exChangeReg0 <= #5 cmd;
// else if( idx == 1 ) exChangeReg1 <= #5 cmd;
// else if( idx == 2 ) exChangeReg2 <= #5 cmd;
// else if( idx == 3 ) exChangeReg3 <= #5 cmd;
// else if( idx == 4 ) exChangeReg4 <= #5 cmd;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// while( transCnt < length ) begin
// if( idx == 0 ) exChangeReg0 <= #5 txBuf[transCnt];
// else if( idx == 1 ) exChangeReg1 <= #5 txBuf[transCnt];
// else if( idx == 2 ) exChangeReg2 <= #5 txBuf[transCnt];
// else if( idx == 3 ) exChangeReg3 <= #5 txBuf[transCnt];
// else if( idx == 4 ) exChangeReg4 <= #5 txBuf[transCnt];
// transCnt <= transCnt + 1;
// repeat(8) begin
// `SCKFRE spi_sck[idx] <= 1'b1;
// if( idx == 0 ) exChangeReg0 <= #5 {exChangeReg0[6:0], spi_miso[idx]};
// else if( idx == 1 ) exChangeReg1 <= #5 {exChangeReg1[6:0], spi_miso[idx]};
// else if( idx == 2 ) exChangeReg2 <= #5 {exChangeReg2[6:0], spi_miso[idx]};
// else if( idx == 3 ) exChangeReg3 <= #5 {exChangeReg3[6:0], spi_miso[idx]};
// else if( idx == 4 ) exChangeReg4 <= #5 {exChangeReg4[6:0], spi_miso[idx]};
// `SCKFRE spi_sck[idx] <= 1'b0;
// end
// rxBuf[transCnt] <= #5
// idx == 0 ? exChangeReg0 :
// idx == 1 ? exChangeReg1 :
// idx == 2 ? exChangeReg2 :
// idx == 3 ? exChangeReg3 :
// exChangeReg4;
// end
// spi_csn[idx] <= 1'b1;
// #2400
// spi_csn[idx] <= 1'b1;
// end
// endtask
task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx ); task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx );
begin begin