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QSPI修正可用

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This commit is contained in:
Ruige Lee
2025-05-14 16:26:20 +08:00
parent 2e186a8365
commit ed9bf22016
3 changed files with 113 additions and 133 deletions
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8
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -230,8 +230,12 @@ trait InterfaceMCUop{ this: InterfaceBase =>
oSpi.io.datar := Mux(cReg.spiSel === 1.U, datar, 0.U)
oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U)
when( isEnW ){
printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrSel)
}
when( isEnR ){
printf(s"SPI/QSPI Readout 0x%x, @0x%x\n", datar, addrSel)
}

22
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -57,8 +57,8 @@ abstract class SpiInterfaceBase extends Module{
val byteSel = Reg(UInt(12.W))
io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & isSpiRead & byteSel >= 3.U
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & isSpiWrite & byteSel >= 3.U
io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exReg
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -73,12 +73,12 @@ abstract class SpiInterfaceBase extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrSel := 0.U
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrSel := exReg
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrSel := Cat(exReg, addrSel(7,0))
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 2.U & bitSel.andR ){
when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrSel := addrSel + 1.U
}
}
@@ -86,7 +86,7 @@ abstract class SpiInterfaceBase extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiCmd := "hFF".U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel.andR ){ //CS为低，且SCK上跳的第0byte
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := exReg
}
@@ -113,8 +113,8 @@ class SSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel.andR ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
exReg := 0.U
} .otherwise{
when( isSpiWrite ){
@@ -149,8 +149,8 @@ class QSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel.andR ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 0.U || byteSel === 1.U ){ //第1、2byte
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
exReg := 0.U
} .otherwise{
when( isSpiWrite ){
@@ -162,7 +162,7 @@ class QSpiInterface extends SpiInterfaceBase{
}
}
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(6 ,4), shiftMOSI(1) )
exReg := Cat( exReg(3,0), shiftMOSI(1) )
}