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重构逻辑关系

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This commit is contained in:
RuigeLee
2024-06-26 12:31:16 +08:00
parent f32e82cd7b
commit eca0931fa3
1 changed files with 20 additions and 69 deletions
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89
src/main/scala/backBoard/Qei.scala
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@@ -43,7 +43,7 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
val isOverflow = for( i <- 0 until 2 ) yield { Wire(Bool()) }
val isCounter32Flip = for( i <- 0 until 2 ) yield { RegNext( counter(i).extract(32)) =/= counter(i).extract(32) }
val isCounter31Flip = for( i <- 0 until 2 ) yield { RegNext( counter(i).extract(31)) =/= counter(i).extract(31) }
val isCounter31Flip = for( i <- 0 until 2 ) yield { (RegNext( counter(i).extract(31)) =/= counter(i).extract(31)) & (RegNext( counter(i).extract(32)) === counter(i).extract(32)) }
for( i <- 0 until 2 ){
@@ -61,78 +61,29 @@ trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
when(isEnable(i)){
when(~is2Phase(i)){ //A Phase only
when( RegNext( phaseA(i) ) & ~phaseA(i) ){
when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) + 1.U
}
isOverflow(i) := isSetVal(i) & isCounter32Flip(i)
} .otherwise{ //AB Phase
when( invDirect(i) ) {
when(isAdvA(i)){
counter(i) := counter(i) - 1.U
} .elsewhen(isAdvB(i)){
counter(i) := counter(i) + 1.U
}
}
} .otherwise{ //AB Phase
when( isMiss(i) ){
printf("Warning! QEI Miss one pulse!\n")
} .elsewhen( isAdvA(i) ){
when( isSign(i) ) {
when( invDirect(i) ){
when( isSetVal(i) & isCounter31Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) - 1.U
}
} .otherwise{
when( isSetVal(i) & isCounter31Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) + 1.U
}
}
} .otherwise{
when( invDirect(i) ){
when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) - 1.U
}
} .otherwise{
when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) + 1.U
}
}
} .otherwise{ //~invDirect(i)
when(isAdvA(i)){
counter(i) := counter(i) + 1.U
} .elsewhen(isAdvB(i)){
counter(i) := counter(i) - 1.U
}
} .elsewhen( isAdvB(i) ){
when( isSign(i) ) {
when( invDirect(i) ){
when( isSetVal(i) & isCounter31Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) + 1.U
}
} .otherwise{
when( isSetVal(i) & isCounter31Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) - 1.U
}
}
} .otherwise{
when( invDirect(i) ){
when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) + 1.U
}
} .otherwise{
when( isSetVal(i) & isCounter32Flip(i) ){
isOverflow(i) := true.B
} .otherwise{
counter(i) := counter(i) - 1.U
}
}
}
} .otherwise{
// assert( isKeep(i) )
}
isOverflow(i) :=
Mux( isSign(i), isSetVal(i) & isCounter31Flip(i), isSetVal(i) & isCounter32Flip(i) )
}
} .otherwise{ //~isEnable