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DP sram替代reg方案，未测试

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This commit is contained in:
RuigeLee
2024-03-27 19:37:54 +08:00
parent fa28a840ad
commit eb47b3e94d
2 changed files with 277 additions and 146 deletions
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367
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -42,26 +42,28 @@ class BackBoardMstBase extends Module{ //10M
val lvdsMst = Module(new Lvds_Bus_Master) val lvdsMst = Module(new Lvds_Bus_Master)
val mirrorDown = Module(new MirrorSRAMDown()) val mirrorDown = Module(new MirrorSRAMDown())
val mirrorUp = Module(new MirrorSRAMUp()) val mirrorUp = Module(new MirrorSRAMUp())
val mirrorReg = Module(new MirrorSRAMDP())
val statusCDRErr = RegInit( false.B ) mirrorReg.io.addrB := DontCare
val statusCRCErr = RegInit( false.B ) mirrorReg.io.datawB := DontCare
val statusLinkErr = RegInit( false.B ) mirrorReg.io.enwB := false.B
val statusSynch = RegInit( false.B )
val statusInit = RegInit( false.B ) // val statusCDRErr = RegInit( false.B )
// val statusCRCErr = RegInit( false.B )
// val statusLinkErr = RegInit( false.B )
// val statusSynch = RegInit( false.B )
// val statusInit = RegInit( false.B )
val ctrlTransmit = RegInit( false.B ) val ctrlTransmit = RegInit( false.B )
val ctrlCDRErr = RegInit( false.B )
val ctrlCRCErr = RegInit( false.B )
val ctrlLinkErr = RegInit( false.B )
val ctrlSynch = RegInit( false.B ) val ctrlSynch = RegInit( false.B )
val ctrlInit = RegInit( false.B ) val ctrlInit = RegInit( false.B )
val ctrlFun = RegInit(0.U(8.W)) val ctrlFun = RegInit(0.U(8.W))
val slvNum = RegInit(0.U(6.W)) val slvNum = RegInit(0.U(6.W))
val slvOffLine = RegInit(0.U(6.W)) // val slvOffLine = RegInit(0.U(6.W))
val linkNum = RegInit(0.U(7.W)) // val linkNum = RegInit(0.U(7.W))
val testReg = RegInit("haa55".U(16.W)) // val testReg = RegInit("haa55".U(16.W))
val interrupt = RegInit(false.B); io.interrupt := interrupt val interrupt = RegInit(false.B); io.interrupt := interrupt
val slaveDataLength = RegInit(((8/8)*32-1).U(8.W)) val slaveDataLength = RegInit(((8/8)*32-1).U(8.W))
@@ -85,6 +87,8 @@ class BackBoardMstBase extends Module{ //10M
mirrorUp.io.clockw := io.oser_pclk.asBool mirrorUp.io.clockw := io.oser_pclk.asBool
mirrorUp.io.clockr := io.ides_pclk.asBool //100M mirrorUp.io.clockr := io.ides_pclk.asBool //100M
mirrorReg.io.clockA := io.ides_pclk.asBool //100M
mirrorReg.io.clockB := io.oser_pclk.asBool //10M
when(interrupt === true.B){ when(interrupt === true.B){
interrupt := false.B interrupt := false.B
@@ -106,60 +110,61 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, reset ){//100M withClockAndReset( io.ides_pclk.asClock, reset ){//100M
// val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B )
// val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B )
// val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B )
// val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )
io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn //fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0) io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn
val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)//(~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) ) val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)
val isAccessSRAM = ~latchAddr.extract(10) val isAccessSRAM = ~latchAddr.extract(10)
val isAccessReg = latchAddr.extract(10) val isAccessReg = latchAddr.extract(10)
val activeAddr = latchAddr(9,0) val activeAddr = latchAddr(9,0)
val regOut = Wire(UInt(16.W)) // val regOut = Wire(UInt(16.W))
mirrorDown.io.enw := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn //isAccessSRAM & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) mirrorDown.io.enw := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn
mirrorDown.io.addrw := activeAddr mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := io.FSMC.ADIn mirrorDown.io.dataw := io.FSMC.ADIn
mirrorUp.io.enr := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn//isAccessSRAM & fsmcCSSync(0) & ~fsmcRDSync(1) & fsmcRDSync(0) mirrorUp.io.enr := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn
mirrorUp.io.addrr := activeAddr mirrorUp.io.addrr := activeAddr
io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar) mirrorReg.io.addrA := activeAddr
mirrorReg.io.datawA := io.FSMC.ADIn
mirrorReg.io.enwA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
// mirrorReg.io.enrA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
regOut := Mux1H(Seq( io.FSMC.ADOut := Mux( isAccessReg, mirrorReg.io.datarA, mirrorUp.io.datar)
( activeAddr === 0.U) ->
Cat( // regOut := Mux1H(Seq(
statusCDRErr , // ( activeAddr === 0.U) ->
statusCRCErr , // Cat(
statusLinkErr, // statusCDRErr ,
statusSynch , // statusCRCErr ,
statusInit // statusLinkErr,
), // statusSynch ,
( activeAddr === 1.U) -> ctrlFun, // statusInit
( activeAddr === 2.U) -> slvNum, // ),
( activeAddr === 3.U) -> slvOffLine, // ( activeAddr === 1.U) -> ctrlFun,
( activeAddr === 4.U) -> testReg, // ( activeAddr === 2.U) -> slvNum,
( activeAddr === 5.U) -> linkNum, // ( activeAddr === 3.U) -> slvOffLine,
( activeAddr === 6.U) -> slaveDataLength, // ( activeAddr === 4.U) -> testReg,
)) // ( activeAddr === 5.U) -> linkNum,
// ( activeAddr === 6.U) -> slaveDataLength,
// ))
when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){ //fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){ // when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){
isReqValid := true.B // isReqValid := true.B
wrRegAddr := activeAddr // wrRegAddr := activeAddr
wrRegData := io.FSMC.ADIn // wrRegData := io.FSMC.ADIn
} // }
when( isReqValid & isAckReady ){ // when( isReqValid & isAckReady ){
isReqValid := false.B // isReqValid := false.B
} // }
@@ -167,93 +172,71 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
//10M //10M
when(~RegNext( io.testIO, false.B ) & io.testIO){ when(~RegNext( io.testIO, false.B ) & io.testIO){
when( ctrlFun === 0.U ){
statusInit := false.B mirrorReg.io.addrB := 1.U
mirrorReg.io.datawB := DontCare
mirrorReg.io.enwB := false.B
when( mirrorReg.io.datarB === 0.U ){
ctrlInit := true.B ctrlInit := true.B
} }
when( ctrlFun === 1.U ){ when( mirrorReg.io.datarB === 1.U ){
statusSynch := false.B
ctrlSynch := true.B ctrlSynch := true.B
} }
when( ctrlFun === 5.U ){ when( mirrorReg.io.datarB === 5.U ){
ctrlTransmit := true.B ctrlTransmit := true.B
} }
} }
when( isAckReady ){
isAckReady := false.B
}
when( isReqValid ){
isAckReady := true.B
when( wrRegAddr === 0.U ){
when( wrRegData.extract(4) ){
statusCDRErr := false.B
}
when( wrRegData.extract(3) ){
statusCRCErr := false.B
}
when( wrRegData.extract(2) ){
statusLinkErr := false.B
}
}
when( wrRegAddr === 1.U ){ // when( isAckReady ){
ctrlFun := wrRegData // isAckReady := false.B
} // }
when( wrRegAddr === 2.U ){ // when( isReqValid ){
slvNum := wrRegData // isAckReady := true.B
}
when( wrRegAddr === 4.U ){ // when( wrRegAddr === 0.U ){
testReg := wrRegData // when( wrRegData.extract(4) ){
} // statusCDRErr := false.B
// }
// when( wrRegData.extract(3) ){
// statusCRCErr := false.B
// }
// when( wrRegData.extract(2) ){
// statusLinkErr := false.B
// }
// }
// when( wrRegAddr === 1.U ){
// ctrlFun := wrRegData
// }
// when( wrRegAddr === 2.U ){
// slvNum := wrRegData
// }
// when( wrRegAddr === 4.U ){
// testReg := wrRegData
// }
// when( wrRegAddr === 6.U ){
// slaveDataLength := wrRegData
// }
// }
when( wrRegAddr === 6.U ){
slaveDataLength := wrRegData
}
} }
}
trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
io.FSMC.ADOut := DontCare
io.FSMC.ADOEn := DontCare
val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
when( powerUpCnt === 500.U ){
ctrlInit := true.B
}
val ( _, isTransmitTimeout ) = Counter(Range( 0,520), statusInit, false.B)
when(isTransmitTimeout){
ctrlTransmit := true.B
}
mirrorDown.io.enw := true.B
mirrorDown.io.addrw := powerUpCnt
mirrorDown.io.dataw := "h5555".U
mirrorUp.io.enr := false.B
mirrorUp.io.addrr := 0.U
}
abstract class BackBoardMstLVDSBase extends BackBoardMstBase abstract class BackBoardMstLVDSBase extends BackBoardMstBase
with BackBoardMstFSMC with BackBoardMstFSMC
// with BackBoardMstSim
{ {
@@ -268,6 +251,8 @@ with BackBoardMstFSMC
lvdsMst.io.tx_start := tx_start lvdsMst.io.tx_start := tx_start
val stateCur = RegInit(15.U(4.W)) val stateCur = RegInit(15.U(4.W))
} }
@@ -280,51 +265,80 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
when( isInitStart ){ when( isInitStart ){
stateCur := 0.U stateCur := 0.U
frame_info_update_en := false.B frame_info_update_en := false.B
slave_type_num := 0.U slave_type_num := 0.U
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 0.U ){ } .elsewhen( stateCur === 0.U ){ //statusInit
stateCur := 1.U stateCur := 1.U
mirrorReg.io.addrB := 7.U
mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){
stateCur := 2.U
mirrorReg.io.addrB := 2.U
slvNum := mirrorReg.io.datarB
} .elsewhen( stateCur === 2.U ){
stateCur := 3.U
mirrorReg.io.addrB := 6.U
slaveDataLength := mirrorReg.io.datarB
}
.elsewhen( stateCur === 3.U ){
stateCur := 4.U
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b00".U(2.W), slvNum ) slave_type_num := Cat( "b00".U(2.W), slvNum )
slaveDataLength := slaveDataLength slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
stateCur := 2.U stateCur := 5.U
timeoutCnt := 0.U timeoutCnt := 0.U
frame_info_update_en := false.B frame_info_update_en := false.B
tx_start := true.B tx_start := true.B
} .elsewhen( stateCur === 2.U ){ } .elsewhen( stateCur === 5.U ){
tx_start := false.B tx_start := false.B
timeoutCnt := timeoutCnt + 1.U timeoutCnt := timeoutCnt + 1.U
when( lvdsMst.io.slave_link_num_valid ){ when( lvdsMst.io.slave_link_num_valid ){
linkNum := lvdsMst.io.slave_link_num //linkNum
stateCur := 3.U mirrorReg.io.addrB := 5.U
statusInit := true.B mirrorReg.io.datawB := lvdsMst.io.slave_link_num
mirrorReg.io.enwB := true.B
stateCur := 6.U
ctrlInit := false.B ctrlInit := false.B
interrupt := true.B interrupt := true.B
} }
when( timeoutCnt === 6000.U ){ when( timeoutCnt === 6000.U ){
linkNum := 0.U stateCur := 6.U
stateCur := 3.U
statusInit := true.B //linkNum
mirrorReg.io.addrB := 5.U
mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B
ctrlInit := false.B ctrlInit := false.B
interrupt := true.B interrupt := true.B
} }
} .elsewhen( stateCur === 3.U ){ } .elsewhen( stateCur === 6.U ){ //statusInit
stateCur := 7.U
mirrorReg.io.addrB := 7.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 7.U ){
} }
} }
@@ -339,35 +353,55 @@ trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
frame_info_update_en := false.B frame_info_update_en := false.B
slave_type_num := 0.U slave_type_num := 0.U
tx_start := false.B tx_start := false.B
}.elsewhen( stateCur === 0.U ){
} .elsewhen( stateCur === 0.U ){ //statusSynch
stateCur := 1.U stateCur := 1.U
mirrorReg.io.addrB := 8.U
mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){ //slvnum
stateCur := 2.U
mirrorReg.io.addrB := 2.U
slvNum := mirrorReg.io.datarB
} .elsewhen( stateCur === 2.U ){ //slaveDataLength
stateCur := 3.U
mirrorReg.io.addrB := 6.U
slaveDataLength := mirrorReg.io.datarB
} .elsewhen( stateCur === 3.U ){
stateCur := 4.U
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b01".U(2.W), slvNum ) slave_type_num := Cat( "b01".U(2.W), slvNum )
slaveDataLength := slaveDataLength slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
stateCur := 2.U stateCur := 5.U
frame_info_update_en := false.B frame_info_update_en := false.B
tx_start := true.B tx_start := true.B
} .elsewhen( stateCur === 2.U ){ } .elsewhen( stateCur === 5.U ){
tx_start := false.B tx_start := false.B
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
stateCur := 3.U stateCur := 6.U
statusSynch := true.B
ctrlSynch := false.B ctrlSynch := false.B
interrupt := true.B interrupt := true.B
} }
} .elsewhen( stateCur === 3.U ){ } .elsewhen( stateCur === 6.U ){
stateCur := 7.U
mirrorReg.io.addrB := 8.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 7.U ){
} } .otherwise{
.otherwise{
} }
} }
@@ -389,35 +423,57 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 0.U ){ //setting } .elsewhen( stateCur === 0.U ){ //statusTransmit
stateCur := 1.U stateCur := 1.U
mirrorReg.io.addrB := 9.U
mirrorReg.io.datawB := 0.U
mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 1.U ){ //slvnum
stateCur := 2.U
mirrorReg.io.addrB := 2.U
slvNum := mirrorReg.io.datarB
} .elsewhen( stateCur === 2.U ){ //slaveDataLength
stateCur := 3.U
mirrorReg.io.addrB := 6.U
slaveDataLength := mirrorReg.io.datarB
} .elsewhen( stateCur === 3.U ){ //setting
stateCur := 4.U
frame_info_update_en := true.B frame_info_update_en := true.B
slave_type_num := Cat( "b10".U(2.W), slvNum ) slave_type_num := Cat( "b10".U(2.W), slvNum )
slaveDataLength := slaveDataLength slaveDataLength := slaveDataLength
tx_start := false.B tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start } .elsewhen( stateCur === 4.U ){ // tx start
stateCur := 2.U stateCur := 5.U
frame_info_update_en := false.B frame_info_update_en := false.B
tx_start := true.B tx_start := true.B
} .elsewhen( stateCur === 2.U ){ //waiting for busy drop } .elsewhen( stateCur === 5.U ){ //waiting for busy drop
tx_start := false.B tx_start := false.B
when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){ when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
stateCur := 3.U stateCur := 6.U
} }
} .elsewhen( stateCur === 3.U ){ } .elsewhen( stateCur === 6.U ){
when( lvdsMst.io.upstream_crc_valid ){ when( lvdsMst.io.upstream_crc_valid ){
stateCur := 4.U stateCur := 7.U
ctrlTransmit := false.B ctrlTransmit := false.B
interrupt := true.B interrupt := true.B
} }
} .elsewhen( stateCur === 7.U ){ //statusTransmit
stateCur := 8.U
mirrorReg.io.addrB := 9.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
} .elsewhen( stateCur === 8.U ){
} .otherwise{ } .otherwise{
} }
@@ -430,7 +486,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
when( isTransStart ){ when( isTransStart ){
addrw := 0.U addrw := 0.U
} .elsewhen( lvdsMst.io.rx_data_valid & ctrlTransmit){ } .elsewhen( lvdsMst.io.rx_data_valid & ctrlTransmit){
assert( (stateCur === 2.U) || (stateCur === 3.U) ) assert( (stateCur === 5.U) || (stateCur === 6.U) )
addrw := addrw + 1.U addrw := addrw + 1.U
} }
@@ -440,7 +496,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
addrr := addrr + 1.U addrr := addrr + 1.U
} }
mirrorDown.io.enr := (stateCur === 1.U || stateCur === 2.U) & ctrlTransmit mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & ctrlTransmit
lvdsMst.io.tx_data_in := mirrorDown.io.datar lvdsMst.io.tx_data_in := mirrorDown.io.datar
mirrorDown.io.addrr := addrr mirrorDown.io.addrr := addrr
@@ -452,18 +508,35 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase => trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
when( lvdsMst.io.closed_loop_err ){ when( lvdsMst.io.closed_loop_err ){
slvOffLine := lvdsMst.io.link_err_location(5,0)
statusLinkErr := true.B //slvOffLine := lvdsMst.io.link_err_location(5,0)
mirrorReg.io.addrB := 3.U
mirrorReg.io.datawB := lvdsMst.io.link_err_location(5,0)
mirrorReg.io.enwB := true.B
} .elsewhen( RegNext(lvdsMst.io.closed_loop_err, false.B)){
//statusLinkErr := true.B
mirrorReg.io.addrB := 10.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
interrupt := true.B interrupt := true.B
} }
when( lvdsMst.io.upstream_cdr_err ){ when( lvdsMst.io.upstream_cdr_err ){
statusCDRErr := true.B // statusCDRErr := true.B
mirrorReg.io.addrB := 11.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
interrupt := true.B interrupt := true.B
} }
when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){ when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
statusCRCErr := true.B // statusCRCErr := true.B
mirrorReg.io.addrB := 12.U
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
interrupt := true.B interrupt := true.B
} }

58
src/main/scala/backBoard/MirrorSRAM.scala
View File

@@ -240,5 +240,63 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDPIO extends Bundle{
val addrA = Input(UInt(10.W))
val datawA = Input( UInt(16.W) )
val datarA = Output( UInt(16.W) )
val enwA = Input(Bool())
val clockA = Input(Bool())
val addrB = Input(UInt(10.W))
val datawB = Input( UInt(16.W) )
val datarB = Output( UInt(16.W) )
val enwB = Input(Bool())
val clockB = Input(Bool())
}
val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO)
setInline("MirrorSRAMDP.v",
"""
| module MirrorSRAMDP(
| input [15:0] datawA,
| input [9:0] addrA,
| input enwA,
| output [15:0] datarA,
| input clockA,
|
| input [15:0] datawB,
| input [9:0] addrB,
| input enwB,
| output [15:0] datarB,
| input clockB
| );
|
| Gowin_DPB your_instance_name(
| .douta(datarA), //output [15:0] douta
| .doutb(datarB), //output [15:0] doutb
| .clka(clockA), //input clka
| .ocea(1'b1), //input ocea
| .cea(1'b1), //input cea
| .reseta(1'b0), //input reseta
| .wrea(enwA), //input wrea
| .clkb(clockB), //input clkb
| .oceb(1'b1), //input oceb
| .ceb(1'b1), //input ceb
| .resetb(1'b0), //input resetb
| .wreb(enwB), //input wreb
| .ada(addrA), //input [3:0] ada
| .dina(datawA), //input [15:0] dina
| .adb(addrB), //input [3:0] adb
| .dinb(datawB) //input [15:0] dinb
| );
|
|endmodule
""".stripMargin)
}