DP sram替代reg方案，未测试

src/main/scala/backBoard/MirrorSRAM.scala

@@ -240,5 +240,63 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
 
 
 
+class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
+
+  class MirrorSRAMDPIO extends Bundle{
+
+      val addrA  = Input(UInt(10.W))
+      val datawA  = Input( UInt(16.W) )
+      val datarA  = Output( UInt(16.W) )
+      val enwA    = Input(Bool())
+      val clockA  = Input(Bool())
+
+
+      val addrB = Input(UInt(10.W))
+      val datawB = Input( UInt(16.W) )
+      val datarB = Output( UInt(16.W) )
+      val enwB   = Input(Bool())
+      val clockB = Input(Bool())
+
+  }
+  val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO)
+
+ setInline("MirrorSRAMDP.v",
+              """
+      | module MirrorSRAMDP(
+      |  	input [15:0]  datawA,
+      |  	input [9:0]   addrA,
+      |  	input enwA,
+      |  	output [15:0] datarA,
+      |  	input clockA,
+      |
+      |  	input [15:0]  datawB,
+      |  	input [9:0]   addrB,
+      |  	input enwB,    
+      |  	output [15:0] datarB,
+      |  	input clockB
+      |  );
+      |  
+      |  Gowin_DPB your_instance_name(
+      |    .douta(datarA), //output [15:0] douta
+      |    .doutb(datarB), //output [15:0] doutb
+      |    .clka(clockA), //input clka
+      |    .ocea(1'b1), //input ocea
+      |    .cea(1'b1), //input cea
+      |    .reseta(1'b0), //input reseta
+      |    .wrea(enwA), //input wrea
+      |    .clkb(clockB), //input clkb
+      |    .oceb(1'b1), //input oceb
+      |    .ceb(1'b1), //input ceb
+      |    .resetb(1'b0), //input resetb
+      |    .wreb(enwB), //input wreb
+      |    .ada(addrA), //input [3:0] ada
+      |    .dina(datawA), //input [15:0] dina
+      |    .adb(addrB), //input [3:0] adb
+      |    .dinb(datawB) //input [15:0] dinb
+      |  );
+      |
+      |endmodule
+    """.stripMargin)
+}