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增加频率差160ppm的测试代码

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bacon
2025-08-29 16:45:11 +08:00
parent 706b9f17e5
commit e9d412561e
3 changed files with 89 additions and 58 deletions
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84
tb/shinTest/ShinTopSpiTb.v
View File

@@ -36,10 +36,12 @@ module ShinTopSpiTb(
reg clock; reg clock;
reg reset; reg reset;
reg clk8x;
reg [15:0] multiCLK; reg [15:0] multiCLK;
reg clock2;
reg [15:0] multiCLK2;
`include "dev_predef.vh" `include "dev_predef.vh"
@@ -370,7 +372,7 @@ ShinTop s_ShinTop_slv3(
initial begin initial begin
clock = 0; clock = 0;
clk8x = 0; clock2 = 0;
reset = 1; reset = 1;
latch0 = 0; latch0 = 0;
@@ -382,14 +384,16 @@ initial begin
spi_csn = {`SPI_CSN_NUM{1'b1}}; //~15'b0; spi_csn = {`SPI_CSN_NUM{1'b1}}; //~15'b0;
#100 #125000
reset <= 1; reset <= 1;
#240 #300000
reset <= 0; reset <= 0;
//#20000000 //#20000000
#1000000000 #100000000000
#100000000000
#100000000000
//#5000000 //#5000000
$display("Time Out !!!"); $display("Time Out !!!");
@@ -398,11 +402,7 @@ initial begin
end end
initial begin initial begin
forever begin #20 clk8x <= ~clk8x; end forever begin #100000 clock <= ~clock; end
end
initial begin
forever begin #80 clock <= ~clock; end
end end
@@ -411,10 +411,28 @@ generate
initial begin initial begin
multiCLK[i] = 0; multiCLK[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin for( integer j = 0; j < i; j = j + 1 ) begin
#20 #25000
; ;
end end
forever begin #80 multiCLK[i] <= ~multiCLK[i]; end forever begin #100000 multiCLK[i] <= ~multiCLK[i]; end
end
end
endgenerate
initial begin
forever begin #100016 clock2 <= ~clock2; end
end
generate
for( genvar i = 0; i < 16; i = i + 1 ) begin
initial begin
multiCLK2[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin
#25004
;
end
forever begin #100016 multiCLK2[i] <= ~multiCLK2[i]; end
end end
end end
endgenerate endgenerate
@@ -437,7 +455,7 @@ always @(negedge reset) begin
_reset_deactive <= 1'b1; _reset_deactive <= 1'b1;
end end
`define SCKFRE #640 `define SCKFRE #800000
reg sck = 0; reg sck = 0;
@@ -512,13 +530,13 @@ end
always @(posedge clock) begin always @(posedge clock) begin
if( isReq & sck == 0 ) begin if( isReq & sck == 0 ) begin
isBusy <= #5 1'b1; isBusy <= #6250 1'b1;
transCnt <= #5 0; transCnt <= #6250 0;
byteCnt <= #5 ~12'b0; byteCnt <= #6250 ~12'b0;
bitCnt <= #5 ~3'b0; bitCnt <= #6250 ~3'b0;
spi_csn[idx] <= #5 1'b0; spi_csn[idx] <= #6250 1'b0;
exChangeRego <= txBuf[0]; exChangeRego <= txBuf[0];
end end
end end
@@ -565,8 +583,8 @@ always @(posedge sck) begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso}; exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end end
end else begin end else begin
isBusy <= #5 1'b0; isBusy <= #6250 1'b0;
spi_csn[idx] <= #5 1'b1; spi_csn[idx] <= #6250 1'b1;
end end
end end
end end
@@ -585,13 +603,13 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
length <= slength + 3; length <= slength + 3;
idx <= sidx; idx <= sidx;
#5 #6250
@(negedge sck) @(negedge sck)
isReq <= 1; isReq <= 1;
@(posedge sck) #5 @(posedge sck) #6250
isReq <= 0; isReq <= 0;
@( negedge isBusy) #1000 @( negedge isBusy) #1250000
begin begin
//$fwrite(spidata_file, "------------%5t------------\n", $realtime); //$fwrite(spidata_file, "------------%5t------------\n", $realtime);
$fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n", $fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n",
@@ -869,13 +887,13 @@ task wait_comm_finished();
length = 8'h07; length = 8'h07;
idx = `IF_IQSPI(0); idx = `IF_IQSPI(0);
#5 #6250
@(negedge sck) @(negedge sck)
isReq <= 1; isReq <= 1;
@(posedge sck) #5 @(posedge sck) #6250
isReq <= 0; isReq <= 0;
@( negedge isBusy) #1000 @( negedge isBusy) #1250000
begin begin
end end
@@ -889,17 +907,17 @@ task wait_comm_finished();
length = 8'h07; length = 8'h07;
idx = `IF_IQSPI(0); idx = `IF_IQSPI(0);
#5 #6250
@(negedge sck) @(negedge sck)
isReq <= 1; isReq <= 1;
@(posedge sck) #5 @(posedge sck) #6250
isReq <= 0; isReq <= 0;
@( negedge isBusy) #1000 @( negedge isBusy) #1250000
begin begin
end end
#2000 #2500000
//$display("%x %x", rxBuf[3], rxBuf[6]); //$display("%x %x", rxBuf[3], rxBuf[6]);
if ((rxBuf[3] & 8'h02) == 8'h02) if ((rxBuf[3] & 8'h02) == 8'h02)
begin begin
@@ -910,7 +928,7 @@ task wait_comm_finished();
$display("error occur"); $display("error occur");
is_run = 0; is_run = 0;
end end
if (($realtime - st) >= 5000000.0) if (($realtime - st) >= 6250000000.0)
begin begin
$display("comm timeout."); $display("comm timeout.");
is_run = 0; is_run = 0;
@@ -922,7 +940,7 @@ endtask
initial begin initial begin
#1000 #1250000
`ifdef ENABLE_REG_RW1_TEST `ifdef ENABLE_REG_RW1_TEST
/*--------------------------------------------------------------------------------------------------------- /*---------------------------------------------------------------------------------------------------------
@@ -1075,7 +1093,7 @@ initial begin
`include "tc_runlist.vh" `include "tc_runlist.vh"
#1000000 #1250000000
$display("Testcase Finished! Time Out !!!"); $display("Testcase Finished! Time Out !!!");
$fclose(spidata_file); $fclose(spidata_file);
$stop; $stop;

12
tb/shinTest/gen_pkt.py
View File

@@ -14,9 +14,9 @@ if __name__ == '__main__':
#add_tc_2_runlist(errorPkt.tc5()) #add_tc_2_runlist(errorPkt.tc5())
#add_tc_2_runlist(errorPkt.tc6()) #add_tc_2_runlist(errorPkt.tc6())
#add_tc_2_runlist(base.tc1()) add_tc_2_runlist(base.tc1())
#add_tc_2_runlist(base.tc2()) add_tc_2_runlist(base.tc2())
#add_tc_2_runlist(base.tc3()) add_tc_2_runlist(base.tc3())
#add_tc_2_runlist(base.tc4()) #add_tc_2_runlist(base.tc4())
#add_tc_2_runlist(base.tc5()) #add_tc_2_runlist(base.tc5())
#add_tc_2_runlist(base.tc6()) #add_tc_2_runlist(base.tc6())
@@ -46,9 +46,9 @@ if __name__ == '__main__':
#add_tc_2_runlist(broadcast.tc3()) #add_tc_2_runlist(broadcast.tc3())
add_tc_2_runlist(sync.tc1()) #add_tc_2_runlist(sync.tc1())
add_tc_2_runlist(sync.tc2()) #add_tc_2_runlist(sync.tc2())
add_tc_2_runlist(sync.tc3()) #add_tc_2_runlist(sync.tc3())
#add_tc_2_runlist(sync.tc4()) #add_tc_2_runlist(sync.tc4())
#add_tc_2_runlist(sync.tc5()) #add_tc_2_runlist(sync.tc5())
#add_tc_2_runlist(sync.tc6()) #add_tc_2_runlist(sync.tc6())

49
tb/shinTest/testcase/environment.py
View File

@@ -168,33 +168,42 @@ def bringup():
add_tc_2_runlist(gen_file_def) add_tc_2_runlist(gen_file_def)
def __GenDevice(id, TerminateNode = False): def __GenDevice(id, TerminateNode = False, diffclk = False):
dout_code = "dDat_w[%d]"%(id + 1, ) dout_code = "dDat_w[%d]"%(id + 1, )
din_code = "uDat_w[%d]"%(id + 1, ) din_code = "uDat_w[%d]"%(id + 1, )
if TerminateNode: if TerminateNode:
dout_code = "" dout_code = ""
din_code = "1'b0" din_code = "1'b0"
#clk = "clock"
clk = "multiCLK[0]"
multiclk = "multiCLK"
if diffclk:
#clk = "clock2"
clk = "multiCLK2[0]"
multiclk = "multiCLK2"
code_device = ("\tShinTop s_ShinTop_slv%d(\n"%(id, ) code_device = ("\tShinTop s_ShinTop_slv%d(\n"%(id, )
+"\t.clock(clock),\n" +"\t.clock(%s),\n"%(clk, )
+"\t.reset(reset | isSoftReset[%d]),\n\n"%(id + 1,) +"\t.reset(reset | isSoftReset[%d]),\n\n"%(id + 1,)
+"\t.io_multiCLK_0(multiCLK[0]),\n" +"\t.io_multiCLK_0(%s[0]),\n"%(multiclk, )
+"\t.io_multiCLK_1(multiCLK[1]),\n" +"\t.io_multiCLK_1(%s[1]),\n"%(multiclk, )
+"\t.io_multiCLK_2(multiCLK[2]),\n" +"\t.io_multiCLK_2(%s[2]),\n"%(multiclk, )
+"\t.io_multiCLK_3(multiCLK[3]),\n" +"\t.io_multiCLK_3(%s[3]),\n"%(multiclk, )
+"\t.io_multiCLK_4(multiCLK[4]),\n" +"\t.io_multiCLK_4(%s[4]),\n"%(multiclk, )
+"\t.io_multiCLK_5(multiCLK[5]),\n" +"\t.io_multiCLK_5(%s[5]),\n"%(multiclk, )
+"\t.io_multiCLK_6(multiCLK[6]),\n" +"\t.io_multiCLK_6(%s[6]),\n"%(multiclk, )
+"\t.io_multiCLK_7(multiCLK[7]),\n" +"\t.io_multiCLK_7(%s[7]),\n"%(multiclk, )
+"\t.io_multiCLK_8(multiCLK[8]),\n" +"\t.io_multiCLK_8(%s[8]),\n"%(multiclk, )
+"\t.io_multiCLK_9(multiCLK[9]),\n" +"\t.io_multiCLK_9(%s[9]),\n"%(multiclk, )
+"\t.io_multiCLK_10(multiCLK[10]),\n" +"\t.io_multiCLK_10(%s[10]),\n"%(multiclk, )
+"\t.io_multiCLK_11(multiCLK[11]),\n" +"\t.io_multiCLK_11(%s[11]),\n"%(multiclk, )
+"\t.io_multiCLK_12(multiCLK[12]),\n" +"\t.io_multiCLK_12(%s[12]),\n"%(multiclk, )
+"\t.io_multiCLK_13(multiCLK[13]),\n" +"\t.io_multiCLK_13(%s[13]),\n"%(multiclk, )
+"\t.io_multiCLK_14(multiCLK[14]),\n" +"\t.io_multiCLK_14(%s[14]),\n"%(multiclk, )
+"\t.io_multiCLK_15(multiCLK[15]),\n\n" +"\t.io_multiCLK_15(%s[15]),\n\n"%(multiclk, )
+"\t.io_dDatIn(dDat_w[%d]),\n"%(id, ) +"\t.io_dDatIn(dDat_w[%d]),\n"%(id, )
+"\t.io_dDatOut(%s),\n"%(dout_code, ) +"\t.io_dDatOut(%s),\n"%(dout_code, )
@@ -292,7 +301,11 @@ def gen_slv_dev_num(num):
code = "" code = ""
for id in range(num - 1): for id in range(num - 1):
if id == 1:
code = code + __GenDevice(id, diffclk = True)
else:
code = code + __GenDevice(id) code = code + __GenDevice(id)
code = code + __GenDevice(num - 1, True) code = code + __GenDevice(num - 1, True)
genPkt.addAfterExc(code) genPkt.addAfterExc(code)