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增加频率差160ppm的测试代码

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bacon
2025-08-29 16:45:11 +08:00
parent 706b9f17e5
commit e9d412561e
3 changed files with 89 additions and 58 deletions
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84
tb/shinTest/ShinTopSpiTb.v
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@@ -36,10 +36,12 @@ module ShinTopSpiTb(
reg clock;
reg reset;
reg clk8x;
reg [15:0] multiCLK;
reg clock2;
reg [15:0] multiCLK2;
`include "dev_predef.vh"
@@ -370,7 +372,7 @@ ShinTop s_ShinTop_slv3(
initial begin
clock = 0;
clk8x = 0;
clock2 = 0;
reset = 1;
latch0 = 0;
@@ -382,14 +384,16 @@ initial begin
spi_csn = {`SPI_CSN_NUM{1'b1}}; //~15'b0;
#100
#125000
reset <= 1;
#240
#300000
reset <= 0;
//#20000000
#1000000000
#100000000000
#100000000000
#100000000000
//#5000000
$display("Time Out !!!");
@@ -398,11 +402,7 @@ initial begin
end
initial begin
forever begin #20 clk8x <= ~clk8x; end
end
initial begin
forever begin #80 clock <= ~clock; end
forever begin #100000 clock <= ~clock; end
end
@@ -411,10 +411,28 @@ generate
initial begin
multiCLK[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin
#20
#25000
;
end
forever begin #80 multiCLK[i] <= ~multiCLK[i]; end
forever begin #100000 multiCLK[i] <= ~multiCLK[i]; end
end
end
endgenerate
initial begin
forever begin #100016 clock2 <= ~clock2; end
end
generate
for( genvar i = 0; i < 16; i = i + 1 ) begin
initial begin
multiCLK2[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin
#25004
;
end
forever begin #100016 multiCLK2[i] <= ~multiCLK2[i]; end
end
end
endgenerate
@@ -437,7 +455,7 @@ always @(negedge reset) begin
_reset_deactive <= 1'b1;
end
`define SCKFRE #640
`define SCKFRE #800000
reg sck = 0;
@@ -512,13 +530,13 @@ end
always @(posedge clock) begin
if( isReq & sck == 0 ) begin
isBusy <= #5 1'b1;
transCnt <= #5 0;
isBusy <= #6250 1'b1;
transCnt <= #6250 0;
byteCnt <= #5 ~12'b0;
bitCnt <= #5 ~3'b0;
byteCnt <= #6250 ~12'b0;
bitCnt <= #6250 ~3'b0;
spi_csn[idx] <= #5 1'b0;
spi_csn[idx] <= #6250 1'b0;
exChangeRego <= txBuf[0];
end
end
@@ -565,8 +583,8 @@ always @(posedge sck) begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end
end else begin
isBusy <= #5 1'b0;
spi_csn[idx] <= #5 1'b1;
isBusy <= #6250 1'b0;
spi_csn[idx] <= #6250 1'b1;
end
end
end
@@ -585,13 +603,13 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
length <= slength + 3;
idx <= sidx;
#5
#6250
@(negedge sck)
isReq <= 1;
@(posedge sck) #5
@(posedge sck) #6250
isReq <= 0;
@( negedge isBusy) #1000
@( negedge isBusy) #1250000
begin
//$fwrite(spidata_file, "------------%5t------------\n", $realtime);
$fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n",
@@ -869,13 +887,13 @@ task wait_comm_finished();
length = 8'h07;
idx = `IF_IQSPI(0);
#5
#6250
@(negedge sck)
isReq <= 1;
@(posedge sck) #5
@(posedge sck) #6250
isReq <= 0;
@( negedge isBusy) #1000
@( negedge isBusy) #1250000
begin
end
@@ -889,17 +907,17 @@ task wait_comm_finished();
length = 8'h07;
idx = `IF_IQSPI(0);
#5
#6250
@(negedge sck)
isReq <= 1;
@(posedge sck) #5
@(posedge sck) #6250
isReq <= 0;
@( negedge isBusy) #1000
@( negedge isBusy) #1250000
begin
end
#2000
#2500000
//$display("%x %x", rxBuf[3], rxBuf[6]);
if ((rxBuf[3] & 8'h02) == 8'h02)
begin
@@ -910,7 +928,7 @@ task wait_comm_finished();
$display("error occur");
is_run = 0;
end
if (($realtime - st) >= 5000000.0)
if (($realtime - st) >= 6250000000.0)
begin
$display("comm timeout.");
is_run = 0;
@@ -922,7 +940,7 @@ endtask
initial begin
#1000
#1250000
`ifdef ENABLE_REG_RW1_TEST
/*---------------------------------------------------------------------------------------------------------
@@ -1075,7 +1093,7 @@ initial begin
`include "tc_runlist.vh"
#1000000
#1250000000
$display("Testcase Finished! Time Out !!!");
$fclose(spidata_file);
$stop;