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cdrin的preamble连续监控10个cycle

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RuigeLee
2025-09-05 15:09:52 +08:00
parent adb1d9c1c8
commit e9bc1d1e18
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -172,7 +172,7 @@ trait CDRInAxis{ this: CDRInBase =>
io.decode.dataIn := checkSFD(9,0)
val shiftData = io.decode.dataOut
val shiftDataNext = RegNext( shiftData, 0.U(8.W) )
val shiftData10Next = ShiftRegister( shiftData, 10, 0.U(8.W), true.B )
val payloadLen = RegInit(0.U(12.W))
@@ -187,7 +187,7 @@ trait CDRInAxis{ this: CDRInBase =>
stateNext :=
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( shiftDataNext === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_IDLE) -> ( Mux( shiftData10Next === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
)) //crc
@@ -197,7 +197,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( stateCurr === STATE_IDLE & ( shiftDataNext === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
when( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
bitCnt := 0.U
} .otherwise{
when( bitCnt === 9.U ){
@@ -209,7 +209,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( io.flush ){
byteCnt := 0.U
} .elsewhen( stateCurr === STATE_IDLE & ( shiftDataNext === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
} .elsewhen( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
byteCnt := 0.U
} .elsewhen( bitCnt === 9.U ){
when( stateCurr === STATE_HEADER ){