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tx 首尾修正

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This commit is contained in:
RuigeLee
2023-10-24 16:27:30 +08:00
parent 701ba16491
commit e99ff4789f
3 changed files with 16 additions and 15 deletions
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16
src/main/scala/Switch/mac/MacTilelink.scala
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@@ -33,7 +33,7 @@ abstract class MacTileLinkBase() extends Module{
val txReq = Decoupled(new TxFifo_Stream_Bundle)
val TxEndFrm_wb = Output(Bool())
// val TxEndFrm_wb = Output(Bool())
// Tx Status signals
@@ -131,7 +131,7 @@ abstract class MacTileLinkBase() extends Module{
val TxStartFrm_wb = RegInit(false.B)
val TxEndFrm_wb = RegInit(false.B); io.TxEndFrm_wb := TxEndFrm_wb
val TxEndFrm_wb = RegInit(false.B)//; io.TxEndFrm_wb := TxEndFrm_wb
val TxLength = RegInit(0.U(16.W))
val LatchedTxLength = RegInit(0.U(16.W))
@@ -151,11 +151,11 @@ abstract class MacTileLinkBase() extends Module{
}
when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
TxEndFrm_wb := true.B
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
TxEndFrm_wb := false.B
}
when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
TxEndFrm_wb := true.B
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
TxEndFrm_wb := false.B
}
when( io.txDeq.req.fire ){
@@ -203,7 +203,7 @@ abstract class MacTileLinkBase() extends Module{
io.txReq.bits.isLast := TxEndFrm_wb
io.txReq.bits.data := io.txDeq.data.bits
io.txReq.bits.isStart := TxStartFrm_wb
io.txReq.valid := io.txDeq.data.valid