diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala index 70c3bee..aa32ec0 100644 --- a/src/main/scala/mac/MAC.scala +++ b/src/main/scala/mac/MAC.scala @@ -11,10 +11,13 @@ import freechips.rocketchip.interrupts._ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{ + + + val tlMasterNode = TLManagerNode(Seq(TLSlavePortParameters.v1( managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0x30000000L, 0x0FFFL)), + address = Seq(AddressSet(0x30000400L, 0x03FFL)), regionType = RegionType.VOLATILE, executable = false, fifoId = Some(2), @@ -39,6 +42,15 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{ val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int)) + val configNode = TLRegisterNode( + address = Seq(AddressSet(0x30000000L, 0x0000ffffL)), + device = dtsdevice, + concurrency = 1, + beatBytes = 32/8, + executable = true + ) + + lazy val module = new MacImp(this) @@ -179,10 +191,8 @@ val miim = Module(new MIIM) -val RegDataOut = Wire(UInt(32.W)) val r_RecSmall = Wire(Bool()) val r_LoopBck = Wire(Bool()) -val r_TxEn = Wire(Bool()) val r_RxEn = Wire(Bool()) val MRxDV_Lb = Wire(Bool()) val MRxErr_Lb = Wire(Bool()) @@ -199,7 +209,6 @@ val r_MAC = Wire(UInt(48.W)) val LoadRxStatus = Wire(Bool()) val r_HASH0 = Wire(UInt(32.W)) val r_HASH1 = Wire(UInt(32.W)) -val r_TxBDNum = Wire(UInt(8.W)) val r_IPGT = Wire(UInt(7.W)) val r_IPGR1 = Wire(UInt(7.W)) val r_IPGR2 = Wire(UInt(7.W)) @@ -211,11 +220,6 @@ val r_NoBckof = Wire(Bool()) val r_ExDfrEn = Wire(Bool()) val r_TxFlow = Wire(Bool()) val r_IFG = Wire(Bool()) -val TxB_IRQ = Wire(Bool()) -val TxE_IRQ = Wire(Bool()) -val RxB_IRQ = Wire(Bool()) -val RxE_IRQ = Wire(Bool()) -val Busy_IRQ = Wire(Bool()) val r_Pad = Wire(Bool()) val r_CrcEn = Wire(Bool()) val r_FullD = Wire(Bool()) @@ -245,12 +249,10 @@ val LateCollLatched = Wire(Bool()) val DeferLatched = Wire(Bool()) val RstDeferLatched = Wire(Bool()) val CarrierSenseLost = Wire(Bool()) -val RegCs = Wire(UInt(4.W)) -dontTouch(RegDataOut ) + dontTouch(r_RecSmall ) dontTouch(r_LoopBck ) -dontTouch(r_TxEn ) dontTouch(r_RxEn ) dontTouch(MRxDV_Lb ) dontTouch(MRxErr_Lb ) @@ -267,7 +269,6 @@ dontTouch(r_MAC ) dontTouch(LoadRxStatus ) dontTouch(r_HASH0 ) dontTouch(r_HASH1 ) -dontTouch(r_TxBDNum ) dontTouch(r_IPGT ) dontTouch(r_IPGR1 ) dontTouch(r_IPGR2 ) @@ -279,11 +280,6 @@ dontTouch(r_NoBckof ) dontTouch(r_ExDfrEn ) dontTouch(r_TxFlow ) dontTouch(r_IFG ) -dontTouch(TxB_IRQ ) -dontTouch(TxE_IRQ ) -dontTouch(RxB_IRQ ) -dontTouch(RxE_IRQ ) -dontTouch(Busy_IRQ ) dontTouch(r_Pad ) dontTouch(r_CrcEn ) dontTouch(r_FullD ) @@ -313,84 +309,68 @@ dontTouch(LateCollLatched ) dontTouch(DeferLatched ) dontTouch(RstDeferLatched ) dontTouch(CarrierSenseLost ) -dontTouch(RegCs ) -val ethReg = Module(new MacReg) - - - ethReg.io.DataIn := slv_bus.a.bits.data - ethReg.io.Address := slv_bus.a.bits.address(9,2) - ethReg.io.Rw := slv_bus.a.bits.opcode === 0.U | slv_bus.a.bits.opcode === 1.U +// val ethReg = Module(new MacReg) -ethReg.io.Cs := RegCs -ethReg.io.WCtrlDataStart := WCtrlDataStart -ethReg.io.RStatStart := RStatStart -ethReg.io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg -ethReg.io.Prsd := Prsd -ethReg.io.NValid_stat := NValid_stat -ethReg.io.Busy_stat := Busy_stat -ethReg.io.LinkFail := LinkFail -ethReg.io.TxB_IRQ := TxB_IRQ -ethReg.io.TxE_IRQ := TxE_IRQ -ethReg.io.RxB_IRQ := RxB_IRQ -ethReg.io.RxE_IRQ := RxE_IRQ -ethReg.io.Busy_IRQ := Busy_IRQ -ethReg.io.RstTxPauseRq := RstTxPauseRq -ethReg.io.TxCtrlEndFrm := TxCtrlEndFrm -ethReg.io.StartTxDone := StartTxDone -ethReg.io.TxClk := io.mtx_clk_pad_i -ethReg.io.RxClk := io.mrx_clk_pad_i -ethReg.io.SetPauseTimer := SetPauseTimer -ethReg.io.dbg_dat := 0.U -RegDataOut := ethReg.io.DataOut -r_RecSmall := ethReg.io.r_RecSmall -r_Pad := ethReg.io.r_Pad -r_HugEn := ethReg.io.r_HugEn -r_CrcEn := ethReg.io.r_CrcEn -r_DlyCrcEn := ethReg.io.r_DlyCrcEn -r_FullD := ethReg.io.r_FullD -r_ExDfrEn := ethReg.io.r_ExDfrEn -r_NoBckof := ethReg.io.r_NoBckof -r_LoopBck := ethReg.io.r_LoopBck -r_IFG := ethReg.io.r_IFG -r_Pro := ethReg.io.r_Pro -r_Bro := ethReg.io.r_Bro -r_NoPre := ethReg.io.r_NoPre -r_TxEn := ethReg.io.r_TxEn -r_RxEn := ethReg.io.r_RxEn -r_HASH0 := ethReg.io.r_HASH0 -r_HASH1 := ethReg.io.r_HASH1 -r_IPGT := ethReg.io.r_IPGT -r_IPGR1 := ethReg.io.r_IPGR1 -r_IPGR2 := ethReg.io.r_IPGR2 -r_MinFL := ethReg.io.r_MinFL -r_MaxFL := ethReg.io.r_MaxFL -r_MaxRet := ethReg.io.r_MaxRet -r_CollValid := ethReg.io.r_CollValid -r_TxFlow := ethReg.io.r_TxFlow -r_RxFlow := ethReg.io.r_RxFlow -r_PassAll := ethReg.io.r_PassAll -r_MiiNoPre := ethReg.io.r_MiiNoPre -r_ClkDiv := ethReg.io.r_ClkDiv -r_WCtrlData := ethReg.io.r_WCtrlData -r_RStat := ethReg.io.r_RStat -r_ScanStat := ethReg.io.r_ScanStat -r_RGAD := ethReg.io.r_RGAD -r_FIAD := ethReg.io.r_FIAD -r_CtrlData := ethReg.io.r_CtrlData -r_MAC := ethReg.io.r_MAC -r_TxBDNum := ethReg.io.r_TxBDNum -// io.int_o := ethReg.io.int_o - int(0) := ethReg.io.int_o -r_TxPauseTV := ethReg.io.r_TxPauseTV -r_TxPauseRq := ethReg.io.r_TxPauseRq + +wishbone.io.WCtrlDataStart := WCtrlDataStart +wishbone.io.RStatStart := RStatStart +wishbone.io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg +wishbone.io.Prsd := Prsd +wishbone.io.NValid_stat := NValid_stat +wishbone.io.Busy_stat := Busy_stat +wishbone.io.LinkFail := LinkFail +wishbone.io.RstTxPauseRq := RstTxPauseRq +wishbone.io.TxCtrlEndFrm := TxCtrlEndFrm +wishbone.io.StartTxDone := StartTxDone +wishbone.io.TxClk := io.mtx_clk_pad_i +wishbone.io.RxClk := io.mrx_clk_pad_i +wishbone.io.SetPauseTimer := SetPauseTimer + + +r_RecSmall := wishbone.io.r_RecSmall +r_Pad := wishbone.io.r_Pad +r_HugEn := wishbone.io.r_HugEn +r_CrcEn := wishbone.io.r_CrcEn +r_DlyCrcEn := wishbone.io.r_DlyCrcEn +r_FullD := wishbone.io.r_FullD +r_ExDfrEn := wishbone.io.r_ExDfrEn +r_NoBckof := wishbone.io.r_NoBckof +r_LoopBck := wishbone.io.r_LoopBck +r_IFG := wishbone.io.r_IFG +r_Pro := wishbone.io.r_Pro +r_Bro := wishbone.io.r_Bro +r_NoPre := wishbone.io.r_NoPre +r_HASH0 := wishbone.io.r_HASH0 +r_HASH1 := wishbone.io.r_HASH1 +r_IPGT := wishbone.io.r_IPGT +r_IPGR1 := wishbone.io.r_IPGR1 +r_IPGR2 := wishbone.io.r_IPGR2 +r_MinFL := wishbone.io.r_MinFL +r_MaxFL := wishbone.io.r_MaxFL +r_MaxRet := wishbone.io.r_MaxRet +r_CollValid := wishbone.io.r_CollValid +r_TxFlow := wishbone.io.r_TxFlow +r_MiiNoPre := wishbone.io.r_MiiNoPre +r_ClkDiv := wishbone.io.r_ClkDiv +r_WCtrlData := wishbone.io.r_WCtrlData +r_RStat := wishbone.io.r_RStat +r_ScanStat := wishbone.io.r_ScanStat +r_RGAD := wishbone.io.r_RGAD +r_FIAD := wishbone.io.r_FIAD +r_CtrlData := wishbone.io.r_CtrlData +r_MAC := wishbone.io.r_MAC +// io.int_o := wishbone.io.int_o + int(0) := wishbone.io.int_o +r_TxPauseTV := wishbone.io.r_TxPauseTV +r_TxPauseRq := wishbone.io.r_TxPauseRq @@ -721,8 +701,8 @@ val rxethmac = Module(new MacRx) wishbone.io.LoadRxStatus := LoadRxStatus wishbone.io.ReceivedPacketGood := ReceivedPacketGood wishbone.io.AddressMiss := AddressMiss - wishbone.io.r_RxFlow := r_RxFlow - wishbone.io.r_PassAll := r_PassAll + r_RxFlow := wishbone.io.r_RxFlow + r_PassAll := wishbone.io.r_PassAll wishbone.io.ReceivedPauseFrm := ReceivedPauseFrm wishbone.io.RetryCntLatched := RetryCntLatched @@ -752,17 +732,7 @@ val rxethmac = Module(new MacRx) wishbone.io.RxAbort := RxAbort_wb RxStatusWriteLatched_sync2 := wishbone.io.RxStatusWriteLatched_sync2 - wishbone.io.r_TxEn := r_TxEn - wishbone.io.r_RxEn := r_RxEn - wishbone.io.r_TxBDNum := r_TxBDNum - wishbone.io.RegDataOut := RegDataOut - RegCs := wishbone.io.RegCs - TxB_IRQ := wishbone.io.TxB_IRQ - TxE_IRQ := wishbone.io.TxE_IRQ - RxB_IRQ := wishbone.io.RxB_IRQ - RxE_IRQ := wishbone.io.RxE_IRQ - Busy_IRQ := wishbone.io.Busy_IRQ - + r_RxEn := wishbone.io.r_RxEn val macstatus = Module(new MacStatus) diff --git a/src/main/scala/mac/MacRegisters.scala b/src/main/scala/mac/MacRegisters.scala index 1c1b356..acb1551 100644 --- a/src/main/scala/mac/MacRegisters.scala +++ b/src/main/scala/mac/MacRegisters.scala @@ -3,320 +3,314 @@ package MAC import chisel3._ import chisel3.util._ -class MacRegIO extends Bundle{ - val DataIn = Input(UInt(32.W)) - val Address = Input(UInt(8.W)) - val Rw = Input(Bool()) - val Cs = Input(UInt(4.W)) - val WCtrlDataStart = Input(Bool()) - val RStatStart = Input(Bool()) - val UpdateMIIRX_DATAReg = Input(Bool()) - val Prsd = Input(UInt(16.W)) - val NValid_stat = Input(Bool()) - val Busy_stat = Input(Bool()) - val LinkFail = Input(Bool()) - val TxB_IRQ = Input(Bool()) - val TxE_IRQ = Input(Bool()) - val RxB_IRQ = Input(Bool()) - val RxE_IRQ = Input(Bool()) - val Busy_IRQ = Input(Bool()) - val RstTxPauseRq = Input(Bool()) - val TxCtrlEndFrm = Input(Bool()) - val StartTxDone = Input(Bool()) - val TxClk = Input(Bool()) - val RxClk = Input(Bool()) - val SetPauseTimer = Input(Bool()) - val dbg_dat = Input(UInt(32.W)) // debug data input - val DataOut = Output(UInt(32.W)) - val r_RecSmall = Output(Bool()) - val r_Pad = Output(Bool()) - val r_HugEn = Output(Bool()) - val r_CrcEn = Output(Bool()) - val r_DlyCrcEn = Output(Bool()) - val r_FullD = Output(Bool()) - val r_ExDfrEn = Output(Bool()) - val r_NoBckof = Output(Bool()) - val r_LoopBck = Output(Bool()) - val r_IFG = Output(Bool()) - val r_Pro = Output(Bool()) - val r_Iam = Output(Bool()) - val r_Bro = Output(Bool()) - val r_NoPre = Output(Bool()) - val r_TxEn = Output(Bool()) - val r_RxEn = Output(Bool()) - val r_HASH0 = Output(UInt(32.W)) - val r_HASH1 = Output(UInt(32.W)) - val r_IPGT = Output(UInt(7.W)) - val r_IPGR1 = Output(UInt(7.W)) - val r_IPGR2 = Output(UInt(7.W)) - val r_MinFL = Output(UInt(16.W)) - val r_MaxFL = Output(UInt(16.W)) - val r_MaxRet = Output(UInt(4.W)) - val r_CollValid = Output(UInt(6.W)) - val r_TxFlow = Output(Bool()) - val r_RxFlow = Output(Bool()) - val r_PassAll = Output(Bool()) - val r_MiiNoPre = Output(Bool()) - val r_ClkDiv = Output(UInt(8.W)) - val r_WCtrlData = Output(Bool()) - val r_RStat = Output(Bool()) - val r_ScanStat = Output(Bool()) - val r_RGAD = Output(UInt(5.W)) - val r_FIAD = Output(UInt(5.W)) - val r_CtrlData = Output(UInt(16.W)) - val r_MAC = Output(UInt(48.W)) - val r_TxBDNum = Output(UInt(8.W)) - val int_o = Output(Bool()) - val r_TxPauseTV = Output(UInt(16.W)) - val r_TxPauseRq = Output(Bool()) - -} - -class MacReg extends Module{ - val io: MacRegIO = IO(new MacRegIO) - - - - val Write = io.Cs & Fill(4, io.Rw) - val Read = io.Cs.orR & ~io.Rw - - val MODER_Sel = ( io.Address === "h0".U ) - val INT_SOURCE_Sel = ( io.Address === "h1".U ) - val INT_MASK_Sel = ( io.Address === "h2".U ) - val IPGT_Sel = ( io.Address === "h3".U ) - val IPGR1_Sel = ( io.Address === "h4".U ) - val IPGR2_Sel = ( io.Address === "h5".U ) - val PACKETLEN_Sel = ( io.Address === "h6".U ) - val COLLCONF_Sel = ( io.Address === "h7".U ) - val CTRLMODER_Sel = ( io.Address === "h9".U ) - val MIIMODER_Sel = ( io.Address === "hA".U ) - val MIICOMMAND_Sel = ( io.Address === "hB".U ) - val MIIADDRESS_Sel = ( io.Address === "hC".U ) - val MIITX_DATA_Sel = ( io.Address === "hD".U ) - val MAC_ADDR0_Sel = ( io.Address === "h10".U ) - val MAC_ADDR1_Sel = ( io.Address === "h11".U ) - val HASH0_Sel = ( io.Address === "h12".U ) - val HASH1_Sel = ( io.Address === "h13".U ) - val TXCTRL_Sel = ( io.Address === "h14".U ) - val RXCTRL_Sel = ( io.Address === "h15".U ) - val DBG_REG_Sel = ( io.Address === "h16".U ) - val TX_BD_NUM_Sel = ( io.Address === "h8".U ) - - - val MODER_Wr = Write(2,0) & Fill(3, MODER_Sel) - val INT_SOURCE_Wr = Write.extract(0) & INT_SOURCE_Sel - val INT_MASK_Wr = Write.extract(0) & INT_MASK_Sel - val IPGT_Wr = Write.extract(0) & IPGT_Sel - val IPGR1_Wr = Write.extract(0) & IPGR1_Sel - val IPGR2_Wr = Write.extract(0) & IPGR2_Sel - val PACKETLEN_Wr = Write & Fill(4, PACKETLEN_Sel) - val COLLCONF_Wr = Cat( Write.extract(2) & COLLCONF_Sel, 0.U(1.W), Write.extract(0) & COLLCONF_Sel) - val CTRLMODER_Wr = Write.extract(0) & CTRLMODER_Sel - val MIIMODER_Wr = Write(1,0) & Fill(2, MIIMODER_Sel) - val MIICOMMAND_Wr = Write.extract(0) & MIICOMMAND_Sel; - val MIIADDRESS_Wr = Write(1,0) & Fill(2, MIIADDRESS_Sel) - val MIITX_DATA_Wr = Write(1,0) & Fill(2, MIITX_DATA_Sel) - val MIIRX_DATA_Wr = io.UpdateMIIRX_DATAReg - val MAC_ADDR0_Wr = Write & Fill(4, MAC_ADDR0_Sel) - val MAC_ADDR1_Wr = Write(1,0) & Fill(2, MAC_ADDR1_Sel) - val HASH0_Wr = Write & Fill(4, HASH0_Sel) - val HASH1_Wr = Write & Fill(4, HASH1_Sel) - val TXCTRL_Wr = Write(2,0) & Fill(3, TXCTRL_Sel) - val TX_BD_NUM_Wr = Write.extract(0) & TX_BD_NUM_Sel & (io.DataIn <= "h80".U) - - - val INT_SOURCEOut = Wire(UInt(32.W)) - val MIISTATUSOut = Cat( io.NValid_stat, io.Busy_stat, io.LinkFail ) +trait MacTileLinkRegister { this: MacTileLinkBase => - val MODEROut = Cat( // MODER Register - RegEnable( io.DataIn.extract(16), 0.U(1.W), MODER_Wr.extract(2) ), - RegEnable( io.DataIn(15,8), "hA0".U(8.W), MODER_Wr.extract(1) ), - RegEnable( io.DataIn( 7,0), 0.U(8.W), MODER_Wr.extract(0) ), - ) + val RecSmall = RegInit(false.B) + val Pad = RegInit(true.B) + val HugEn = RegInit(false.B) + val CrcEn = RegInit(true.B) + val DlyCrcEn = RegInit(false.B) + + val FullD = RegInit(false.B) + val ExDfrEn = RegInit(false.B) + val NoBckof = RegInit(false.B) + val LoopBck = RegInit(false.B) + val IFG = RegInit(false.B) + val Pro = RegInit(false.B) + val Iam = RegInit(false.B) + val Bro = RegInit(false.B) + val NoPre = RegInit(false.B) + val TxEn = RegInit(false.B) + val RxEn = RegInit(false.B) + + // Interrupt generation + val irq_txb = RegInit(false.B) + val irq_txe = RegInit(false.B) + val irq_rxb = RegInit(false.B) + val irq_rxe = RegInit(false.B) + val irq_busy = RegInit(false.B) + val irq_txc = RegInit(false.B) + val irq_rxc = RegInit(false.B) + + + + when(TxB_IRQ){ irq_txb := true.B } + when(TxE_IRQ){ irq_txe := true.B } + when(RxB_IRQ){ irq_rxb := true.B } + when(RxE_IRQ){ irq_rxe := true.B } + when(Busy_IRQ){ irq_busy := true.B } + when(SetTxCIrq){ irq_txc := true.B } + when(SetRxCIrq){ irq_rxc := true.B } + + val INT_MASK = RegInit(0.U(7.W)) // INT_MASK Register + val IPGT = RegInit("h12".U(7.W)) // IPGT Register + val IPGR1 = RegInit("h0C".U(7.W)) // IPGR1 Register + val IPGR2 = RegInit("h12".U(7.W)) + + val maxFL = RegInit("h0600".U(16.W)) + val minFL = RegInit("h0040".U(16.W)) + + val collValid = RegInit("h3f".U(6.W)) + val maxRet = RegInit("hF".U(4.U)) + + val TX_BD_NUM = RegInit("h40".U(8.W)) // TX_BD_NUM Register + + val txFlow = RegInit(false.B) + val rxFlow = RegInit(false.B) + val passAll = RegInit(false.B) + + val clkDiv = RegInit("h64".U(8.W)) + val miiNoPre = RegInit(false.B) - val INT_MASKOut = RegEnable(io.DataIn(6,0), 0.U(7.W), INT_MASK_Wr) // INT_MASK Register - val IPGTOut = RegEnable(io.DataIn(6,0), "h12".U(7.W), IPGT_Wr ) // IPGT Register - val IPGR1Out = RegEnable(io.DataIn(6,0), "h0C".U(7.W), IPGR1_Wr) // IPGR1 Register - val IPGR2Out = RegEnable(io.DataIn(6,0), "h12".U(7.W), IPGR2_Wr) + val scanStat = RegInit(false.B) + val readStat = RegInit(false.B) + val wCtrlData = RegInit(false.B) + when(io.RStatStart){ readStat := false.B } + when(io.WCtrlDataStart){ wCtrlData := false.B } - val PACKETLENOut = Cat( // PACKETLEN Register - RegEnable(io.DataIn(31,24), 0.U(8.W), PACKETLEN_Wr.extract(3)), - RegEnable(io.DataIn(23,16), "h40".U(8.W), PACKETLEN_Wr.extract(2)), - RegEnable(io.DataIn(15,8 ), 6.U(8.W), PACKETLEN_Wr.extract(1)), - RegEnable(io.DataIn( 7,0 ), 0.U(8.W), PACKETLEN_Wr.extract(0)) - ) + val FIAD = RegInit(0.U(5.W)) + val RGAD = RegInit(0.U(5.W)) - val COLLCONFOut = Cat( // COLLCONF Register - RegEnable(io.DataIn(19,16), "hF".U(4.W), COLLCONF_Wr.extract(2)), - 0.U(10.W), - RegEnable(io.DataIn(5,0), "h3f".U(6.W), COLLCONF_Wr.extract(0)) - ) + val MIITX_DATA = RegInit(0.U(16.W)) // MIITX_DATA Register - val TX_BD_NUMOut = RegEnable(io.DataIn(7,0), "h40".U(8.W), TX_BD_NUM_Wr) // TX_BD_NUM Register - val CTRLMODEROut = RegEnable(io.DataIn(2,0), 0.U(3.W), CTRLMODER_Wr.extract(0)) // CTRLMODER Register + val MIIRX_DATA = RegEnable(io.Prsd, 0.U(16.W), io.UpdateMIIRX_DATAReg) // MIIRX_DATA Register - val MIIMODEROut = Cat( // MIIMODER Register - RegEnable(io.DataIn.extract(8), 0.U(1.W), MIIMODER_Wr.extract(1)), - RegEnable(io.DataIn(7,0), "h64".U(8.W), MIIMODER_Wr.extract(0)) - ) + val Mac_ADDR0 = RegInit(0.U(32.W)) + val Mac_ADDR1 = RegInit(0.U(16.W)) - val MIICOMMANDOut0 = RegEnable(io.DataIn.extract(0), 0.U(1.W), MIICOMMAND_Wr) - val MIICOMMANDOut1 = RegInit(false.B) - val MIICOMMANDOut2 = RegInit(false.B) + val HASH0 = RegInit(0.U(32.W)) + val HASH1 = RegInit(0.U(32.W)) - when(io.RStatStart){ - MIICOMMANDOut1 := false.B - } .elsewhen(MIICOMMAND_Wr){ - MIICOMMANDOut1 := io.DataIn.extract(1) - } + val txPauseRq = RegInit(false.B) + val txPauseTV = RegInit(0.U(16.W)) - when(io.WCtrlDataStart){ - MIICOMMANDOut2 := false.B - } .elsewhen(MIICOMMAND_Wr){ - MIICOMMANDOut2 := io.DataIn.extract(2) - } - val MIICOMMANDOut = Cat(MIICOMMANDOut2, MIICOMMANDOut1, MIICOMMANDOut0) // MIICOMMAND Register - - - val MIIADDRESSOut = Cat( // MIIADDRESSRegister - RegEnable(io.DataIn(12,8), 0.U(5.W), MIIADDRESS_Wr.extract(1)), - 0.U(3.W), - RegEnable(io.DataIn( 4,0), 0.U(5.W), MIIADDRESS_Wr.extract(0)) - ) - - - val MIITX_DATAOut = Cat( // MIITX_DATA Register - RegEnable(io.DataIn(15,8), 0.U(8.W), MIITX_DATA_Wr.extract(1)), - RegEnable(io.DataIn( 7,0), 0.U(8.W), MIITX_DATA_Wr.extract(0)) - ) - - val MIIRX_DATAOut = RegEnable(io.Prsd, 0.U(16.W), MIIRX_DATA_Wr) // MIIRX_DATA Register - - val MAC_ADDR0Out = Cat( // MAC_ADDR0 Register - RegEnable(io.DataIn(31,24), 0.U(8.W), MAC_ADDR0_Wr.extract(3)), - RegEnable(io.DataIn(23,16), 0.U(8.W), MAC_ADDR0_Wr.extract(2)), - RegEnable(io.DataIn(15, 8), 0.U(8.W), MAC_ADDR0_Wr.extract(1)), - RegEnable(io.DataIn(7 , 0), 0.U(8.W), MAC_ADDR0_Wr.extract(0)) - ) - - val MAC_ADDR1Out = Cat( // MAC_ADDR1 Register - RegEnable(io.DataIn(15,8), 0.U(8.W), MAC_ADDR1_Wr.extract(1)), - RegEnable(io.DataIn(7 ,0), 0.U(8.W), MAC_ADDR1_Wr.extract(0)) - ) + when( io.RstTxPauseRq ){ txPauseRq := false.B } - val HASH0Out = Cat( // RXHASH0 Register - RegEnable(io.DataIn(31,24), 0.U(8.W), HASH0_Wr.extract(3)), - RegEnable(io.DataIn(23,16), 0.U(8.W), HASH0_Wr.extract(2)), - RegEnable(io.DataIn(15, 8), 0.U(8.W), HASH0_Wr.extract(1)), - RegEnable(io.DataIn(7 , 0), 0.U(8.W), HASH0_Wr.extract(0)) - ) - - val HASH1Out = Cat( // RXHASH1 Register - RegEnable(io.DataIn(31,24), 0.U(8.W), HASH1_Wr.extract(3)), - RegEnable(io.DataIn(23,16), 0.U(8.W), HASH1_Wr.extract(2)), - RegEnable(io.DataIn(15, 8), 0.U(8.W), HASH1_Wr.extract(1)), - RegEnable(io.DataIn(7 , 0), 0.U(8.W), HASH1_Wr.extract(0)) - ) - val TXCTRLOut16 = RegInit(false.B) - when( io.RstTxPauseRq ){ - TXCTRLOut16 := false.B - } .elsewhen( TXCTRL_Wr.extract(2) ){ - TXCTRLOut16 := io.DataIn.extract(16) - } - - val TXCTRLOut = Cat( // TXCTRL Register - TXCTRLOut16, - RegEnable(io.DataIn(15,8), 0.U(8.W), TXCTRL_Wr.extract(1)), - RegEnable(io.DataIn(7, 0), 0.U(8.W), TXCTRL_Wr.extract(0)) - ) - - - - // Reading data from registers - io.DataOut := - Mux( - Read, - Mux1H(Seq( - (io.Address === 0.U ) -> MODEROut, - (io.Address === 1.U ) -> INT_SOURCEOut, - (io.Address === 2.U ) -> INT_MASKOut, - (io.Address === 3.U ) -> IPGTOut, - (io.Address === 4.U ) -> IPGR1Out, - (io.Address === 5.U ) -> IPGR2Out, - (io.Address === 6.U ) -> PACKETLENOut, - (io.Address === 7.U ) -> COLLCONFOut, - (io.Address === 9.U ) -> CTRLMODEROut, - (io.Address === 10.U ) -> MIIMODEROut, - (io.Address === 11.U ) -> MIICOMMANDOut, - (io.Address === 12.U ) -> MIIADDRESSOut, - (io.Address === 13.U ) -> MIITX_DATAOut, - (io.Address === 14.U ) -> MIIRX_DATAOut, - (io.Address === 15.U ) -> MIISTATUSOut, - (io.Address === 16.U ) -> MAC_ADDR0Out, - (io.Address === 17.U ) -> MAC_ADDR1Out, - (io.Address === 8.U ) -> TX_BD_NUMOut, - (io.Address === 18.U ) -> HASH0Out, - (io.Address === 19.U ) -> HASH1Out, - (io.Address === 20.U ) -> TXCTRLOut, - (io.Address === 22.U ) -> io.dbg_dat, + configNode.regmap( + ( 0.U << 2 ) -> + RegFieldGroup("MODER", Some("Mode Register"), Seq( + RegField(1, RxEn , RegFieldDesc( "RxEn", "RxEn", reset = Some(0))) , + RegField(1, TxEn , RegFieldDesc( "TxEn", "TxEn", reset = Some(0) ) ), + RegField(1, NoPre , RegFieldDesc( "NoPre", "NoPre", reset = Some(0) ) ), + RegField(1, Bro , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ), + RegField(1, Iam , RegFieldDesc( "Iam", "Iam", reset = Some(0) ) ), + RegField(1, Pro , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ), + RegField(1, IFG , RegFieldDesc( "IFG", "IFG", reset = Some(0) ) ), + RegField(1, LoopBck, RegFieldDesc( "LoopBck", "LoopBck", reset = Some(0) ) ), + RegField(1, NoBckof, RegFieldDesc( "NoBckof", "NoBckof", reset = Some(0) ) ), + RegField(1, ExDfrEn, RegFieldDesc( "ExDfrEn", "ExDfrEn", reset = Some(0) ) ), + RegField(1, FullD , RegFieldDesc( "FullD", "FullD", reset = Some(0) ) ), + RegField.r(1), + RegField(1, DlyCrcEn, RegFieldDesc( "DlyCrcEn", "DlyCrcEn", reset=Some(0)) ), + RegField(1, CrcEn , RegFieldDesc( "CrcEn", "CrcEn", reset=Some(1)) ), + RegField(1, HugEn , RegFieldDesc( "HugEn", "HugEn", reset=Some(0)) ), + RegField(1, Pad , RegFieldDesc( "Pad", "Pad", reset=Some(1)) ), + RegField(1, RecSmall, RegFieldDesc( "RecSmall", "RecSmall", reset=Some(0)) ) )), - 0.U - ) + + ( 1.U << 2 ) -> + RegFieldGroup("INT_SOURCE", Some("Interrupt Source Register"), Seq( + RegField(1, irq_txb, RegWriteFn((valid, data) => { when (valid & data) { irq_txb := 0.U }; true.B }), RegFieldDesc("txb", "txb", reset=Some(0))), + RegField(1, irq_txe, RegWriteFn((valid, data) => { when (valid & data) { irq_txe := 0.U }; true.B }), RegFieldDesc("txe", "txe", reset=Some(0))), + RegField(1, irq_rxb, RegWriteFn((valid, data) => { when (valid & data) { irq_rxb := 0.U }; true.B }), RegFieldDesc("rxb", "rxb", reset=Some(0))), + RegField(1, irq_rxe, RegWriteFn((valid, data) => { when (valid & data) { irq_rxe := 0.U }; true.B }), RegFieldDesc("rxe", "rxe", reset=Some(0))), + RegField(1, irq_busy, RegWriteFn((valid, data) => { when (valid & data) { irq_busy := 0.U }; true.B }), RegFieldDesc("busy", "busy", reset=Some(0))), + RegField(1, irq_txc, RegWriteFn((valid, data) => { when (valid & data) { irq_txc := 0.U }; true.B }), RegFieldDesc("txc", "txc", reset=Some(0))), + RegField(1, irq_rxc, RegWriteFn((valid, data) => { when (valid & data) { irq_rxc := 0.U }; true.B }), RegFieldDesc("rxc", "rxc", reset=Some(0))), + )), + + ( 2.U << 2 ) -> + RegFieldGroup("INT_MASK", Some("Interrupt Mask Register"), Seq( + RegField(7, INT_MASK) + )), + + ( 3.U << 2 ) -> + RegFieldGroup("IPGT", Some("Back to Back Inter Packet Gap Register"), Seq( + RegField(7, IPGT, RegFieldDesc("IPGT", "IPGT", reset=Some(0x12))) + )), + + ( 4.U << 2 ) -> + RegFieldGroup("IPGR1", Some("Non Back to Back Inter Packet Gap Register 1"), Seq( + RegField(7, IPGR1, RegFieldDesc("IPGR1", "IPGR1", reset=Some(0xc))) + )), + + ( 5.U << 2 ) -> + RegFieldGroup("IPGR2", Some("Non Back to Back Inter Packet Gap Register 2"), Seq( + RegField(7, IPGR2, RegFieldDesc("IPGR2", "IPGR2", reset=Some(0x12))) + )), + + ( 6.U << 2 ) -> + RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq( + RegField(16, maxFL, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))), + RegField(16, minFL, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))), + )), + ( 7.U << 2 ) -> + RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq( + RegField(6, collValid, RegFieldDesc("collValid", "Collision Valid", reset=Some(0x3f))), + RegField.r(10), + RegField(4, maxRet, RegFieldDesc("maxRet", "Maximum Retry", reset=Some(0xf))), + )), + + ( 8.U << 2 ) -> + RegFieldGroup("TX_BD_NUM", Some("Transmit BD Number Register"), Seq( + RegField(8, TX_BD_NUM, RegFieldDesc("TX_BD_NUM", "TX_BD_NUM", reset=Some(0x40))), + )), + + ( 9.U << 2 ) -> + RegFieldGroup("CTRLMODER", Some("Control Module Mode Register"), Seq( + RegField(1, passAll, RegFieldDesc("PassAll", "Pass All Receive Frames", reset=Some(0))), + RegField(1, rxFlow , RegFieldDesc("RxFlow", "Receive Flow Control", reset=Some(0))), + RegField(1, txFlow , RegFieldDesc("TxFlow", "Transmit Flow Control", reset=Some(0))), + )), + + ( 10.U << 2 ) -> + RegFieldGroup("MIIMODER", Some("MII Mode Register"), Seq( + RegField(8, clkDiv, RegFieldDesc("clkDiv", "Clock Divider", reset=Some(0x64))), + RegField(1, miiNoPre, RegFieldDesc("MIINoPre", "NO Preamble", reset=Some(0x0))), + )), + + ( 11.U << 2 ) -> + RegFieldGroup("MIICOMMAND", Some("MII Command Register"), Seq( + RegField(1, scanStat, RegFieldDesc("scanStat", "Scan Status", reset=Some(0x0))), + RegField(1, readStat, RegFieldDesc("readStat", "Read Status", reset=Some(0x0))), + RegField(1, wCtrlStat, RegFieldDesc("wCtrlStat", "Write Control Status", reset=Some(0x0))), + )), + + ( 12.U << 2 ) -> + RegFieldGroup("MIIADDRESS", Some("MII Address Register"), Seq( + RegField(5, FIAD, RegFieldDesc("FIAD", "PHY Address", reset=Some(0x0))), + RegField.r(3), + RegField(5, RGAD, RegFieldDesc("RGAD", "Register Address", reset=Some(0x0))), + )), + + ( 13.U << 2 ) -> + RegFieldGroup("MIITX_DATA", Some("MII Transmit Data"), Seq( + RegField(16, MIITX_DATA) + )), + + ( 14.U << 2 ) -> MIIRX_DATAOut + RegFieldGroup("MIIRX_DATA", Some("MII Receive Data"), Seq( + RegField.r(16, MIIRX_DATA) + )), + + ( 15.U << 2 ) -> + RegFieldGroup("MIISTATUS", Some("MII Status Register"), Seq( + RegField.r(1, io.LinkFail), + RegField.r(1, io.Busy_stat), + RegField.r(1, io.NValid_stat), + )), + + ( 16.U << 2 ) -> + RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq( + RegField(32, MAC_ADDR0) + )), + + ( 17.U << 2 ) -> + RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq( + RegField(16, MAC_ADDR1) + )), + + ( 18.U << 2 ) -> + RegFieldGroup("HASH0", Some("HASH Register 0"), Seq( + RegField(32, HASH0) + )), + + ( 19.U << 2 ) -> + RegFieldGroup("HASH1", Some("HASH Register 1"), Seq( + RegField(32, HASH1) + )), + + ( 20.U << 2 ) ->, + RegFieldGroup("TXCTRL", Some("Tx Control Register"), Seq( + RegField(16, txPauseTV, RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0))), + RegField(1, txPauseRq, RegFieldDesc("TxPauseRQ", "Tx Pause Request", reset=Some(0x0))), + )), + ) + + + + + + io.r_RecSmall := RecSmall + io.r_Pad := Pad + io.r_HugEn := HugEn + io.r_CrcEn := CrcEn + io.r_DlyCrcEn := DlyCrcEn + io.r_FullD := FullD + io.r_ExDfrEn := ExDfrEn + io.r_NoBckof := NoBckof + io.r_LoopBck := LoopBck + io.r_IFG := IFG + io.r_Pro := Pro + io.r_Iam := Iam + io.r_Bro := Bro + io.r_NoPre := NoPre + val r_TxEn = TxEn & (TX_BD_NUM > 0.U) // Transmission is enabled when there is at least one TxBD. + io.r_RxEn := RxEn & (TX_BD_NUM < "h80".U) // Reception is enabled when there is at least one RxBD. + + io.r_IPGT := IPGT + io.r_IPGR1 := IPGR1 + io.r_IPGR2 := IPGR2 + io.r_MinFL := minFL + io.r_MaxFL := maxFL + io.r_MaxRet := maxRet + io.r_CollValid := collValid + io.r_TxFlow := txFlow + io.r_RxFlow := rxFlow + io.r_PassAll := passAll + io.r_MiiNoPre := miiNoPre + io.r_ClkDiv := clkDiv + io.r_WCtrlData := wCtrlData + io.r_RStat := readStat + io.r_ScanStat := scanStat + io.r_RGAD := RGAD + io.r_FIAD := FIAD + io.r_CtrlData := MIITX_DATA + + io.r_MAC := Cat( MAC_ADDR1(15,0), MAC_ADDR0(31,0) ) + io.r_HASH1 := HASH1 + io.r_HASH0 := HASH0 + val r_TxBDNum = TX_BD_NUM + io.r_TxPauseTV := txPauseTV + io.r_TxPauseRq := txPauseRq + + + + + + + + + + + + + + + + + + + + + + + - io.r_RecSmall := MODEROut.extract(16) - io.r_Pad := MODEROut.extract(15) - io.r_HugEn := MODEROut.extract(14) - io.r_CrcEn := MODEROut.extract(13) - io.r_DlyCrcEn := MODEROut.extract(12) - io.r_FullD := MODEROut.extract(10) - io.r_ExDfrEn := MODEROut.extract( 9) - io.r_NoBckof := MODEROut.extract( 8) - io.r_LoopBck := MODEROut.extract( 7) - io.r_IFG := MODEROut.extract( 6) - io.r_Pro := MODEROut.extract( 5) - io.r_Iam := MODEROut.extract( 4) - io.r_Bro := MODEROut.extract( 3) - io.r_NoPre := MODEROut.extract( 2) - io.r_TxEn := MODEROut.extract( 1) & (TX_BD_NUMOut > 0.U) // Transmission is enabled when there is at least one TxBD. - io.r_RxEn := MODEROut.extract( 0) & (TX_BD_NUMOut < "h80".U) // Reception is enabled when there is at least one RxBD. - io.r_IPGT := IPGTOut - io.r_IPGR1 := IPGR1Out - io.r_IPGR2 := IPGR2Out - io.r_MinFL := PACKETLENOut(31,16) - io.r_MaxFL := PACKETLENOut(15, 0) - io.r_MaxRet := COLLCONFOut(19,16) - io.r_CollValid := COLLCONFOut( 5, 0) - io.r_TxFlow := CTRLMODEROut.extract(2) - io.r_RxFlow := CTRLMODEROut.extract(1) - io.r_PassAll := CTRLMODEROut.extract(0) - io.r_MiiNoPre := MIIMODEROut.extract(8) - io.r_ClkDiv := MIIMODEROut(7,0) - io.r_WCtrlData := MIICOMMANDOut.extract(2) - io.r_RStat := MIICOMMANDOut.extract(1) - io.r_ScanStat := MIICOMMANDOut.extract(0) - io.r_RGAD := MIIADDRESSOut(12,8) - io.r_FIAD := MIIADDRESSOut( 4,0) - io.r_CtrlData := MIITX_DATAOut(15,0) - io.r_MAC := Cat( MAC_ADDR1Out(15,0), MAC_ADDR0Out(31,0) ) - io.r_HASH1 := HASH1Out - io.r_HASH0 := HASH0Out - io.r_TxBDNum := TX_BD_NUMOut - io.r_TxPauseTV := TXCTRLOut(15,0) - io.r_TxPauseRq := TXCTRLOut.extract(16) val SetTxCIrq_txclk_wire = Wire(Bool()) @@ -333,60 +327,8 @@ class MacReg extends Module{ - // Interrupt generation - val irq_txb = RegInit(false.B) - val irq_txe = RegInit(false.B) - val irq_rxb = RegInit(false.B) - val irq_rxe = RegInit(false.B) - val irq_busy = RegInit(false.B) - val irq_txc = RegInit(false.B) - val irq_rxc = RegInit(false.B) - when(io.TxB_IRQ){ - irq_txb := true.B - }.elsewhen(INT_SOURCE_Wr & io.DataIn.extract(0)){ - irq_txb := false.B - } - - when(io.TxE_IRQ){ - irq_txe := true.B - } .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(1)){ - irq_txe := false.B - } - - - when(io.RxB_IRQ){ - irq_rxb := true.B - } .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(2)){ - irq_rxb := false.B - } - - - when(io.RxE_IRQ){ - irq_rxe := true.B - } .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(3)){ - irq_rxe := false.B - } - - when(io.Busy_IRQ){ - irq_busy := true.B - } .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(4)){ - irq_busy := false.B - } - - - when(SetTxCIrq){ - irq_txc := true.B - } .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(5)){ - irq_txc := false.B - } - - when(SetRxCIrq){ - irq_rxc := true.B - } .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(6)){ - irq_rxc := false.B - } withClockAndReset( io.TxClk.asClock, reset ) { @@ -423,16 +365,14 @@ class MacReg extends Module{ // Generating interrupt signal io.int_o := - (irq_txb & INT_MASKOut.extract(0) ) | - (irq_txe & INT_MASKOut.extract(1) ) | - (irq_rxb & INT_MASKOut.extract(2) ) | - (irq_rxe & INT_MASKOut.extract(3) ) | - (irq_busy & INT_MASKOut.extract(4) ) | - (irq_txc & INT_MASKOut.extract(5) ) | - (irq_rxc & INT_MASKOut.extract(6) ) + (irq_txb & INT_MASK.extract(0) ) | + (irq_txe & INT_MASK.extract(1) ) | + (irq_rxb & INT_MASK.extract(2) ) | + (irq_rxe & INT_MASK.extract(3) ) | + (irq_busy & INT_MASK.extract(4) ) | + (irq_txc & INT_MASK.extract(5) ) | + (irq_rxc & INT_MASK.extract(6) ) - // For reading interrupt status - INT_SOURCEOut := Cat( irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb ) } diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala index 5dc447b..66f5d83 100644 --- a/src/main/scala/mac/MacTilelink.scala +++ b/src/main/scala/mac/MacTilelink.scala @@ -42,8 +42,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val LoadRxStatus = Input(Bool()) // Rx status was loaded val ReceivedPacketGood = Input(Bool()) // Received packet's length and CRC are good val AddressMiss = Input(Bool()) // When a packet is received AddressMiss status is written to the Rx BD - val r_RxFlow = Input(Bool()) - val r_PassAll = Input(Bool()) val ReceivedPauseFrm = Input(Bool()) // Tx Status signals @@ -76,21 +74,67 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val RxAbort = Input(Bool()) // This signal is set when address doesn't match. val RxStatusWriteLatched_sync2 = Output(Bool()) - //Register - val r_TxEn = Input(Bool()) // Transmit enable - val r_RxEn = Input(Bool()) // Receive enable - val r_TxBDNum = Input(UInt(8.W)) // Receive buffer descriptor number - val RegDataOut = Input(UInt(32.W)) - val RegCs = Output(UInt(4.W)) + //Register + val RegDataOut = Input(UInt(32.W)) - // Interrupts - val TxB_IRQ = Output(Bool()) - val TxE_IRQ = Output(Bool()) - val RxB_IRQ = Output(Bool()) - val RxE_IRQ = Output(Bool()) - val Busy_IRQ = Output(Bool()) + + val WCtrlDataStart = Input(Bool()) + val RStatStart = Input(Bool()) + val UpdateMIIRX_DATAReg = Input(Bool()) + val Prsd = Input(UInt(16.W)) + val NValid_stat = Input(Bool()) + val Busy_stat = Input(Bool()) + val LinkFail = Input(Bool()) + val RstTxPauseRq = Input(Bool()) + val TxCtrlEndFrm = Input(Bool()) + val StartTxDone = Input(Bool()) + val TxClk = Input(Bool()) + val RxClk = Input(Bool()) + val SetPauseTimer = Input(Bool()) + + // val DataOut = Output(UInt(32.W)) + val r_RecSmall = Output(Bool()) + val r_Pad = Output(Bool()) + val r_HugEn = Output(Bool()) + val r_CrcEn = Output(Bool()) + val r_DlyCrcEn = Output(Bool()) + val r_FullD = Output(Bool()) + val r_ExDfrEn = Output(Bool()) + val r_NoBckof = Output(Bool()) + val r_LoopBck = Output(Bool()) + val r_IFG = Output(Bool()) + val r_Pro = Output(Bool()) + val r_Iam = Output(Bool()) + val r_Bro = Output(Bool()) + val r_NoPre = Output(Bool()) + val r_RxEn = Output(Bool()) + val r_HASH0 = Output(UInt(32.W)) + val r_HASH1 = Output(UInt(32.W)) + val r_IPGT = Output(UInt(7.W)) + val r_IPGR1 = Output(UInt(7.W)) + val r_IPGR2 = Output(UInt(7.W)) + val r_MinFL = Output(UInt(16.W)) + val r_MaxFL = Output(UInt(16.W)) + val r_MaxRet = Output(UInt(4.W)) + val r_CollValid = Output(UInt(6.W)) + val r_TxFlow = Output(Bool()) + val r_RxFlow = Output(Bool()) + val r_PassAll = Output(Bool()) + val r_MiiNoPre = Output(Bool()) + val r_ClkDiv = Output(UInt(8.W)) + val r_WCtrlData = Output(Bool()) + val r_RStat = Output(Bool()) + val r_ScanStat = Output(Bool()) + val r_RGAD = Output(UInt(5.W)) + val r_FIAD = Output(UInt(5.W)) + val r_CtrlData = Output(UInt(16.W)) + val r_MAC = Output(UInt(48.W)) + val int_o = Output(Bool()) + val r_TxPauseTV = Output(UInt(16.W)) + val r_TxPauseRq = Output(Bool()) + } @@ -103,10 +147,10 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val BDCs = Wire(UInt(4.W)) - val TxB_IRQ = RegInit(false.B); io.TxB_IRQ := TxB_IRQ - val TxE_IRQ = RegInit(false.B); io.TxE_IRQ := TxE_IRQ - val RxB_IRQ = RegInit(false.B); io.RxB_IRQ := RxB_IRQ - val RxE_IRQ = RegInit(false.B); io.RxE_IRQ := RxE_IRQ + val TxB_IRQ = RegInit(false.B) + val TxE_IRQ = RegInit(false.B) + val RxB_IRQ = RegInit(false.B) + val RxE_IRQ = RegInit(false.B) @@ -197,8 +241,8 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val RxEn_q = RegNext(RxEn, false.B) val TxEn = RegInit(false.B) val TxEn_q = RegNext(TxEn, false.B) - val r_TxEn_q = RegNext(io.r_TxEn, false.B) - val r_RxEn_q = RegNext(io.r_RxEn, false.B) + val r_TxEn_q = RegNext(r_TxEn, false.B) + val r_RxEn_q = RegNext(r_RxEn, false.B) val ram_ce = true.B val ram_we = Wire(UInt(4.W)) @@ -323,7 +367,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod (RxEn & RxEn_q & (RxBDRead | RxPointerRead)) - when(~TxBDReady & io.r_TxEn & WbEn & ~WbEn_q){ + when(~TxBDReady & r_TxEn & WbEn & ~WbEn_q){ TxEn_needed := true.B } .elsewhen(TxPointerRead & TxEn & TxEn_q){ TxEn_needed := false.B @@ -644,11 +688,11 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod // Temporary Tx and Rx buffer descriptor address//[7:1] val TempTxBDAddress = Mux( TxStatusWrite & ~WrapTxStatusBit, (TxBDAddress + 1.U), 0.U ) // Tx BD increment or wrap (last BD) - val TempRxBDAddress = Mux( WrapRxStatusBit, io.r_TxBDNum(6,0), (RxBDAddress + 1.U) ) // Using first Rx BD / Using next Rx BD + val TempRxBDAddress = Mux( WrapRxStatusBit, r_TxBDNum(6,0), (RxBDAddress + 1.U) ) // Using first Rx BD / Using next Rx BD // Latching Tx buffer descriptor address - when(io.r_TxEn & (~r_TxEn_q)){ + when(r_TxEn & (~r_TxEn_q)){ TxBDAddress := 0.U } .elsewhen(TxStatusWrite){ TxBDAddress := TempTxBDAddress @@ -656,7 +700,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod // Latching Rx buffer descriptor address when(io.r_RxEn & (~r_RxEn_q)){ - RxBDAddress := io.r_TxBDNum(6,0) + RxBDAddress := r_TxBDNum(6,0) } .elsewhen(RxStatusWrite){ RxBDAddress := TempRxBDAddress; } @@ -846,7 +890,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod )) - when(~RxReady & io.r_RxEn & WbEn & ~WbEn_q){ + when(~RxReady & r_RxEn & WbEn & ~WbEn_q){ RxEn_needed := true.B } .elsewhen(RxPointerRead & RxEn & RxEn_q){ RxEn_needed := false.B @@ -964,14 +1008,14 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod } // Rx Done Interrupt - when(RxStatusWrite & RxIRQEn & io.ReceivedPacketGood & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){ + when(RxStatusWrite & RxIRQEn & io.ReceivedPacketGood & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & passAll & (~rxFlow))){ RxB_IRQ := (~RxError) } .otherwise{ RxB_IRQ := false.B } // Rx Error Interrupt - when(RxStatusWrite & RxIRQEn & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){ + when(RxStatusWrite & RxIRQEn & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & passAll & (~rxFlow))){ RxE_IRQ := RxError } .otherwise{ RxE_IRQ := false.B @@ -989,14 +1033,18 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod - // Connected to registers - val CsMiss = Wire(Bool()) - io.RegCs := Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & ~io.tlSlv.A.bits.address(11) & ~io.tlSlv.A.bits.address(10)) & io.tlSlv.A.bits.mask // 0x0 - 0x3FF + + // // Connected to registers + // val CsMiss = Wire(Bool()) + + + + val RegCs = Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & ~io.tlSlv.A.bits.address(11) & ~io.tlSlv.A.bits.address(10)) & io.tlSlv.A.bits.mask // 0x0 - 0x3FF BDCs := Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & ~io.tlSlv.A.bits.address(11) & io.tlSlv.A.bits.address(10)) & io.tlSlv.A.bits.mask // 0x400 - 0x7FF - CsMiss := io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & io.tlSlv.A.bits.address(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid. + // CsMiss := io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & io.tlSlv.A.bits.address(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid. val slvAInfo = RegEnable( io.tlSlv.A.bits, io.tlSlv.A.fire ) val slvDValid = RegInit(false.B); io.tlSlv.D.valid := slvDValid @@ -1008,7 +1056,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod slvDValid := false.B } .elsewhen(io.tlSlv.A.fire){ slvDValid := true.B - slvDDat := Mux( ((io.RegCs.orR) & io.tlSlv.A.bits.opcode === 4.U), io.RegDataOut, BD_WB_DAT_O ) + slvDDat := Mux( ((RegCs.orR) & io.tlSlv.A.bits.opcode === 4.U), io.RegDataOut, BD_WB_DAT_O ) } when(slvAInfo.opcode === 4.U) { @@ -1017,16 +1065,12 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod io.tlSlv.D.bits := edgeIn.AccessAck(slvAInfo) } - io.tlSlv.A.ready := RegNext(io.RegCs.orR & ~io.tlSlv.A.fire, false.B) | BDAck + io.tlSlv.A.ready := RegNext(RegCs.orR & ~io.tlSlv.A.fire, false.B) | BDAck assert( ~(io.tlSlv.A.ready & ~io.tlSlv.A.valid) ) - when( io.tlSlv.A.fire & (~(io.tlSlv.A.bits.mask.orR) | CsMiss) ){ - assert( false.B, "Assert Failed, tileLink access an undefine region!" ) - } - - - - + // when( io.tlSlv.A.fire & (~(io.tlSlv.A.bits.mask.orR) | CsMiss) ){ + // assert( false.B, "Assert Failed, tileLink access an undefine region!" ) + // }