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写完软件需要加gpio

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This commit is contained in:
Ruige Lee (WSL)
2025-01-16 16:34:48 +08:00
parent f63e3a831b
commit e54ddab4e2
9 changed files with 419 additions and 572 deletions
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66
tb/verilator/SimTop.v
View File

@@ -84,7 +84,7 @@ ExampleRocketSystem s_rocket_mst(
.cdrio_dDatOut(dDatSer[0])
);
/*
ExampleRocketSystem s_rocket_slv0(
.clock(clock),
.reset(reset),
@@ -254,7 +254,7 @@ ExampleRocketSystem s_rocket_slv2(
.cdrio_dDatIn(dDatSer[2]),
.cdrio_dDatOut()
);
*/
@@ -317,6 +317,12 @@ ExampleRocketSystem s_rocket_slv2(
initial begin
s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 0;
s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 1;
s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 2;
s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 3;
end
string testName;
@@ -339,7 +345,7 @@ initial begin
#20
$readmemh("./tb/sw/build/mstTest.verilog", mem0);
for ( i = 0; i < DP; i = i + 1 ) begin
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem0[i*4+0] || mem0[i*4+1] || mem0[i*4+2] || mem0[i*4+3] ) begin
`MEM0[i] = {mem0[i*4+3], mem0[i*4+2], mem0[i*4+1], mem0[i*4+0]};
end
@@ -350,35 +356,35 @@ initial begin
// $display("MEM0[%d] = %h", i, `MEM0[i]);
end
// $readmemh("./tb/sw/build/slvTest.verilog", mem1);
// for ( i = 0; i < DP; i = i + 1 ) begin
// if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
// `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
// end
// else begin
// `MEM1[i] = 32'h0;
// end
// end
$readmemh("./tb/sw/build/slvTest.verilog", mem1);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
`MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
end
else begin
`MEM1[i] = 32'h0;
end
end
// $readmemh("./tb/sw/build/slvTest.verilog", mem2);
// for ( i = 0; i < DP; i = i + 1 ) begin
// if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
// `MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
// end
// else begin
// `MEM2[i] = 32'h0;
// end
// end
$readmemh("./tb/sw/build/slvTest.verilog", mem2);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
`MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
end
else begin
`MEM2[i] = 32'h0;
end
end
// $readmemh("./tb/sw/build/slvTest.verilog", mem3);
// for ( i = 0; i < DP; i = i + 1 ) begin
// if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
// `MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
// end
// else begin
// `MEM3[i] = 32'h0;
// end
// end
$readmemh("./tb/sw/build/slvTest.verilog", mem3);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
`MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
end
else begin
`MEM3[i] = 32'h0;
end
end
end

17
tb/verilator/plusarg_reader.v Normal file
View File

@@ -0,0 +1,17 @@
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),
// but Incisive demands them. These default values should never be used.
module plusarg_reader #(
parameter FORMAT="borked=%d",
parameter WIDTH=1,
parameter [WIDTH-1:0] DEFAULT=0
) (
output [WIDTH-1:0] out
);
assign out = DEFAULT;
endmodule