ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dma cache to sys-port

Browse Source
This commit is contained in:
RuigeLee
2023-09-20 11:17:30 +08:00
parent 8a9aa0436c
commit e42c6a3b11
1 changed files with 7 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/mac/WithMac.scala
View File

@@ -12,7 +12,7 @@ trait WithManyMacMix { this: BaseSubsystem =>
val mac0 = LazyModule(new Mac)
mbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
sbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
pbus.coupleTo("mac_cfg") { mac0.tlMasterNode := TLFragmenter(pbus) := _ }
pbus.coupleTo("mac_cfg") { mac0.ethReg.configNode := TLFragmenter(pbus) := _ }
@@ -28,6 +28,12 @@ trait WithManyMacMixModuleImp extends LazyModuleImp {
macIO <> outer.mac0.module.io
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
}
class MacConfig() extends Config((site, here, up) => {