a new top for fpga; port mac-master to mem

2023-07-17 21:41:34 +08:00
parent de5eb461f6
commit e3e1f6b6cb
3 changed files with 319 additions and 6 deletions
--- a/tb/sw/axi_uart/uart.c
+++ b/tb/sw/axi_uart/uart.c
@@ -28,13 +28,10 @@ int32_t uart_init()

 int32_t uart_sendByte( uint8_t data )
 {
-
+	uint64_t sent = (uint64_t)data << 32;
+	#if(0)
 	//wait unitl tx fifo not full
 	while( ((*uart_status) & 0x08) != 0);
-
-	uint64_t sent = (uint64_t)data << 32;
-
-	#if(0)
 	(*(volatile uint64_t*)(UART_BASE)) = sent;
 	#else
 	(*(volatile uint64_t*)(0x60000000)) = sent;