a new top for fpga; port mac-master to mem

2023-07-17 21:41:34 +08:00
parent de5eb461f6
commit e3e1f6b6cb
3 changed files with 319 additions and 6 deletions
--- a/src/main/scala/mac/WithMac.scala
+++ b/src/main/scala/mac/WithMac.scala
@@ -13,7 +13,7 @@ trait WithManyMacMix { this: BaseSubsystem =>
    val mac0 = LazyModule(new Mac)

    fbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
-    pbus.coupleTo("mac_cfg")   { mac0.tlMasterNode := TLFragmenter(pbus) := _ }
+    mbus.coupleTo("mac_cfg")   { mac0.tlMasterNode := TLFragmenter(pbus) := _ }

    ibus.fromSync := mac0.int_node