ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

优化spi，更严谨

Browse Source
This commit is contained in:
RuigeLee
2025-09-09 18:06:14 +08:00
parent ba04725e72
commit e258cd4a6c
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -99,8 +99,8 @@ class SSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳 when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
spiCmd := 0.U spiCmd := 0.U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(2) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(2) spiCmd := shiftMOSI(1)
} }
@@ -178,8 +178,8 @@ class QSpiInterface extends SpiInterfaceBase{
when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳 when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
spiCmd := 0.U spiCmd := 0.U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(2) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(2).extract(3) spiCmd := shiftMOSI(1).extract(3)
} }
when( shiftCSn(2) & ~shiftCSn(1) ){ when( shiftCSn(2) & ~shiftCSn(1) ){