spi面积通过

src/main/scala/backBoard/MirrorSRAM.scala

@@ -4,124 +4,6 @@ import chisel3._
 import chisel3.util._
 
 
-// class MirrorSRAM(dw: Int,  cl: Int) extends RawModule {
-//   def line_w   = log2Ceil(cl)
-//   val io = IO(new Bundle{
-//     val addrr  = Input(UInt(line_w.W))
-//     val addrw  = Input(UInt(line_w.W))
-
-//     val dataw = Input( UInt(dw.W) )
-//     val datar = Output( UInt(dw.W) )
-//     val enw   = Input(Bool())
-//     val enr   = Input(Bool())
-
-//     val clock = Input(Bool())
-//     val reset = Input(Bool())
-//   })
-
-
-//   withClockAndReset( io.clock.asClock, io.reset ){
-//     val mem = SyncReadMem( cl, UInt(dw.W) )
-
-
-
-
-//     io.datar := DontCare
-//     when( io.enr ) {
-//       io.datar := mem.read( io.addrr )
-//     } 
-//     when( io.enw ) {
-//       mem.write( io.addrw, io.dataw )
-//     }
-//   }
-
-
-
-
-// }
-
-
-
-
-
-
-
-//     val addrr  = Input(UInt(line_w.W))
-//     val addrw  = Input(UInt(line_w.W))
-
-//     val dataw = Input( UInt(dw.W) )
-//     val datar = Output( UInt(dw.W) )
-//     val enw   = Input(Bool())
-//     val enr   = Input(Bool())
-
-//     val clock = Input(Bool())
-//     val reset = Input(Bool())
-
-
-// class MirrorSRAM(dw: Int,  cl: Int) extends BlackBox with HasBlackBoxInline {
-//   require(dw == 8)
-//   require(cl == 2048)
-//   class MirrorSRAMIO extends Bundle{
-//       val addrr  = Input(UInt(11.W))
-//       val addrw  = Input(UInt(11.W))
-
-//       val dataw = Input( UInt(8.W) )
-//       val datar = Output( UInt(8.W) )
-//       val enw   = Input(Bool())
-//       val enr   = Input(Bool())
-
-//       val clockr = Input(Bool())
-//       val clockw = Input(Bool())
-
-//   }
-//   val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
-
-//  setInline("MirrorSRAM.v",
-//               """
-//       | module MirrorSRAM(
-//       |  	input [7:0]  dataw,
-//       |  	input [10:0] addrw,
-//       |  	input enw,
-//       |  
-//       |  	output [7:0] datar,
-//       |  	input [10:0] addrr,
-//       |  	input enr,
-//       |  
-//       |  	input clockr,
-//       |   input clockw
-//       |  );
-//       |  
-//       |  	reg [7:0] ram[0:2047];
-//       |  	reg [7:0] data_r_reg;
-//       |  
-//       |  			always @(posedge clockw) begin
-//       |  				if(enw) begin
-//       |  					ram[addrw] <= #1 dataw;					
-//       |  				end
-//       |       end
-//       |  
-//       |       always @(posedge clockr) begin
-//       |  				if(enr) begin
-//       |  					data_r_reg <= #1 ram[addrr];
-//       |  				end
-//       |  			end
-//       |  
-//       |  	assign datar = data_r_reg;
-//       |  
-//       |  initial begin
-//       |  	for ( integer i = 0; i < 2048; i = i + 1 ) begin
-//       |  		ram[i] = $random;
-//       |  	end
-//       |  
-//       |  	data_r_reg = $random;
-//       |  end
-//       |   
-//       |endmodule
-//     """.stripMargin)
-// }
-
-
-
 
 class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
   class MirrorSRAMDownIO extends Bundle{
@@ -337,13 +219,15 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
 
 
 
-class MirrorSRAMSpi() extends BlackBox with HasBlackBoxInline {
-  class MirrorSRAMSpiIO extends Bundle{
-      val addrr  = Input(UInt(4.W))
-      val addrw  = Input(UInt(4.W))
 
-      val dataw = Input( UInt(248.W) )
+
-      val datar = Output( UInt(248.W) )
+class SpiSRAMDown() extends BlackBox with HasBlackBoxInline {
+  class SpiSRAMDownIO extends Bundle{
+      val addrr  = Input(UInt(9.W))
+      val addrw  = Input(UInt(9.W))
+
+      val dataw = Input(  UInt(8.W) )
+      val datar = Output( UInt(8.W) )
       val enw   = Input(Bool())
       val enr   = Input(Bool())
 
@@ -351,39 +235,92 @@ class MirrorSRAMSpi() extends BlackBox with HasBlackBoxInline {
       val clockw = Input(Bool())
 
   }
-  val io: MirrorSRAMSpiIO = IO(new MirrorSRAMSpiIO)
+  val io: SpiSRAMDownIO = IO(new SpiSRAMDownIO)
 
- setInline("MirrorSRAMSpi.v",
+ setInline("SpiSRAMDown.v",
               """
-      | module MirrorSRAMSpi(
+      | module SpiSRAMDown(
-      |  	input [3:0] addrr,
+      |  	input [7:0] dataw,
-      |  	input [3:0] addrw,
+      |  	input [8:0] addrw,
-      |
-      |  	input [247:0] dataw,
-      |  	output [247:0] datar,
       |  	input enw,
+      |  
+      |  	output [7:0] datar,
+      |  	input [8:0] addrr,
       |  	input enr,
       |  
       |  	input clockr,
-      |  	input clockw
+      |   input clockw
       |  );
       |  
-      |  	reg [247:0] ram[0:15];
+      |  	reg [7:0] ram[0:511];
-      |  	reg [247:0] data_r_reg;
+      |  	reg [7:0] data_r_reg;
       |  
-      |  	always @(posedge clockw) begin
+      |  			always @(posedge clockw) begin
-      |  		if(enw) begin
+      |  				if(enw) begin
-      |  			ram[addrw] <= #1 dataw;					
+      |  					ram[addrw] <= #1 dataw;					
-      |  		end
+      |  				end
-      |   end
+      |       end
-      | 
-      |
-      |   always @(posedge clockr) begin
-      |     if(enr) begin
-      |  		  data_r_reg <= #1 ram[addrr];
-      |     end
-      |   end
       |  
+      |       always @(posedge clockr) begin
+      |  				if(enr) begin
+      |  					data_r_reg <= #1 ram[addrr];
+      |  				end
+      |  			end
+      |  
+      |  	assign datar = data_r_reg;
+      |  
+      |   
+      |endmodule
+    """.stripMargin)
+}
+
+
+class SpiSRAMUp extends BlackBox with HasBlackBoxInline {
+
+  class SpiSRAMUpIO extends Bundle{
+      val addrr  = Input(UInt(9.W))
+      val addrw  = Input(UInt(9.W))
+
+      val dataw = Input( UInt(8.W) )
+      val datar = Output( UInt(8.W) )
+      val enw   = Input(Bool())
+      val enr   = Input(Bool())
+
+      val clockr = Input(Bool())
+      val clockw = Input(Bool())
+
+  }
+  val io: SpiSRAMUpIO = IO(new SpiSRAMUpIO)
+
+ setInline("SpiSRAMUp.v",
+              """
+      | module SpiSRAMUp(
+      |  	input [7:0]  dataw,
+      |  	input [8:0] addrw,
+      |  	input enw,
+      |  
+      |  	output [7:0] datar,
+      |  	input [8:0] addrr,
+      |  	input enr,
+      |  
+      |  	input clockr,
+      |   input clockw
+      |  );
+      |  
+      |  	reg [7:0] ram[0:511];
+      |  	reg [7:0] data_r_reg;
+      |  
+  		|   always @(posedge clockw) begin
+  		|     if(enw) begin
+      |       ram[addrw] <= #1 dataw;
+      |     end
+      |   end
+      |  
+      |   always @(posedge clockr) begin
+      |  		if(enr) begin
+      |  			data_r_reg <= #1 ram[addrr];
+      |  		end
+      |  	end
       |  
       |  	assign datar = data_r_reg;
       |  

src/main/scala/backBoard/SpiSlv.scala

@@ -13,16 +13,19 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
   val csn   = Wire(Bool())
   val clk100M = Wire(Bool())
 
-  val localReg = Module(new MirrorSRAMSpi)
+  val spiRegDown = Module(new SpiSRAMDown)
-  localReg.io.clockw := clock.asBool
+  val spiRegUp   = Module(new SpiSRAMUp)
-  localReg.io.clockr := clock.asBool
+
-  localReg.io.addrr := statusPage
+
-  localReg.io.enr   := true.B
+  spiRegDown.io.clockr := clk100M
+  spiRegDown.io.clockw := clock.asBool
+
+  spiRegUp.io.clockr := clock.asBool
+  spiRegUp.io.clockw := clk100M
+
 
   val localUpdate = RegInit(0.U(16.W))
 
-
-
   val shiftSCK  = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
   val shiftCSn  = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
   val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
@@ -32,30 +35,60 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
   val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
 
 
-  val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt((8*31).W)) }
+  val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
+  val exMask_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(16.W)) }
   val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
   val pageSel = cmd_100M(7,4)
   val spiCmd  = cmd_100M(3,0)
 
+  val bitSel  = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(3.W)) }
+  val byteSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(5.W)) }
 
-  val cnt_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(4.W)) }
 
+  spiRegDown.io.addrr := Cat(pageSel, byteSel)
+  spiRegDown.io.enr := spiCmd === 0.U
+
+  spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
+  spiRegUp.io.dataw := exReg_100M
+  spiRegUp.io.enw   := isSckNegedge & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
      
   withClockAndReset( clk100M.asClock, reset ){//100M
 
     when( shiftCSn(2) & ~shiftCSn(1) ){
-      cnt_100M := 0.U
+      bitSel   := 0.U
-      // misoReg := false.B
+      byteSel  := 0.U
-    } .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M < 8.U ){
+    } .elsewhen( isSckPosedge & ~shiftCSn(1)  ){
-      cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
+      bitSel := bitSel + 1.U
-      cnt_100M := cnt_100M + 1.U
+      when( bitSel === 7.U ){
-    } .elsewhen( isSckNegedge & ~shiftCSn(1) & cnt_100M === 8.U ){
+        byteSel := byteSel + 1.U
-      exReg_100M := Mux( spiCmd.extract(1), Cat( localUpdate, 0.U((8*29).W) ), localReg.io.datar )
+      }
-      cnt_100M := cnt_100M + 1.U
-    } .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M === 9.U ){
-      // misoReg := exReg_100M.extract(exReg_100M.getWidth-1)
-      exReg_100M := Cat( exReg_100M(exReg_100M.getWidth-2 ,0), shiftMOSI(1) )
     }
+
+    when( shiftCSn(2) & ~shiftCSn(1) ){
+      bitSel   := 0.U
+      byteSel  := 0.U
+      cmd_100M := 0.U
+      exReg_100M := 0.U
+    } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){
+      cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
+    } .elsewhen( isSckNegedge & ~shiftCSn(1) & bitSel === 0.U ){
+      when( byteSel === 2.U & spiCmd === 2.U ){
+        exReg_100M := localUpdate(7,0)
+      } .elsewhen( byteSel === 3.U & spiCmd === 2.U ){
+        exReg_100M := localUpdate(15,8)
+      } .elsewhen( spiCmd === 0.U ){
+        exReg_100M := spiRegDown.io.datar
+      }
+    } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel =/= 0.U ){
+      exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
+    }
+
+    when(  isSckNegedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U & spiCmd === 3.U ){
+      exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
+    } .elsewhen(  isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
+      exMask_100M := Cat( exMask_100M(15,8), exReg_100M )
+    }
+
   }
 }
 
@@ -83,40 +116,26 @@ with BackBoardSpiSlv{
   val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B)
 
 
-
   when( isCrcPass ){
     localUpdate := localUpdate & ~( 1.U << downRegTemp(0)(3,0) )
-  } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 3.U ){
+  } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) ){
-    localUpdate := localUpdate & (~exReg_100M(15,0))
+    localUpdate := localUpdate & ~exMask_100M
   }
   
 
   
 
+  spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & downCnt =/= 0.U
+  spiRegDown.io.dataw := io.lvdsSlv.downstream_rx_data_out
+  spiRegDown.io.addrw := Cat( downRegTemp(0)(3,0), downCnt(4,0))
+
+  spiRegUp.io.enr := io.lvdsSlv.upstream_tx_data_ready
+  spiRegUp.io.addrr := Cat( statusPage, upCnt(4,0)+1.U )
 
 
+  io.lvdsSlv.upstream_tx_data_in :=
+    Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
 
-  // for( i <- 0 until page ){
-
-    when( isCrcPass ){
-      localReg.io.addrw := downRegTemp(0)(3,0)
-      localReg.io.enw   := true.B
-      localReg.io.dataw := Cat( (1 until 32).map{ i => downRegTemp(i) }.reverse )
-    } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 1.U ){
-      localReg.io.addrw := pageSel
-      localReg.io.enw   := true.B
-      localReg.io.dataw := exReg_100M
-    } .otherwise{
-      localReg.io.addrw := DontCare
-      localReg.io.enw   := false.B
-      localReg.io.dataw := DontCare
-    }
-
-
-
-    for( i <- 0 until 31 ) {
-      upReg(i+1) := localReg.io.datar((30-i)*8+7, (30-i)*8)
-    }
 
 
 }