spi面积通过
This commit is contained in:
RuigeLee
@@ -13,16 +13,19 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
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val csn = Wire(Bool())
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val clk100M = Wire(Bool())
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val localReg = Module(new MirrorSRAMSpi)
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localReg.io.clockw := clock.asBool
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localReg.io.clockr := clock.asBool
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localReg.io.addrr := statusPage
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localReg.io.enr := true.B
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val spiRegDown = Module(new SpiSRAMDown)
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val spiRegUp = Module(new SpiSRAMUp)
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spiRegDown.io.clockr := clk100M
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spiRegDown.io.clockw := clock.asBool
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spiRegUp.io.clockr := clock.asBool
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spiRegUp.io.clockw := clk100M
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val localUpdate = RegInit(0.U(16.W))
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val shiftSCK = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
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val shiftCSn = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
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val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
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@@ -32,30 +35,60 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
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val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
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val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt((8*31).W)) }
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val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
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val exMask_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(16.W)) }
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val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
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val pageSel = cmd_100M(7,4)
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val spiCmd = cmd_100M(3,0)
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val cnt_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(4.W)) }
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val bitSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(3.W)) }
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val byteSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(5.W)) }
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spiRegDown.io.addrr := Cat(pageSel, byteSel)
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spiRegDown.io.enr := spiCmd === 0.U
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spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
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spiRegUp.io.dataw := exReg_100M
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spiRegUp.io.enw := isSckNegedge & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
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withClockAndReset( clk100M.asClock, reset ){//100M
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when( shiftCSn(2) & ~shiftCSn(1) ){
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cnt_100M := 0.U
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// misoReg := false.B
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M < 8.U ){
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cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
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cnt_100M := cnt_100M + 1.U
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} .elsewhen( isSckNegedge & ~shiftCSn(1) & cnt_100M === 8.U ){
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exReg_100M := Mux( spiCmd.extract(1), Cat( localUpdate, 0.U((8*29).W) ), localReg.io.datar )
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cnt_100M := cnt_100M + 1.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M === 9.U ){
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// misoReg := exReg_100M.extract(exReg_100M.getWidth-1)
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exReg_100M := Cat( exReg_100M(exReg_100M.getWidth-2 ,0), shiftMOSI(1) )
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bitSel := 0.U
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byteSel := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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bitSel := bitSel + 1.U
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when( bitSel === 7.U ){
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byteSel := byteSel + 1.U
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}
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){
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bitSel := 0.U
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byteSel := 0.U
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cmd_100M := 0.U
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exReg_100M := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){
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cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
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} .elsewhen( isSckNegedge & ~shiftCSn(1) & bitSel === 0.U ){
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when( byteSel === 2.U & spiCmd === 2.U ){
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exReg_100M := localUpdate(7,0)
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} .elsewhen( byteSel === 3.U & spiCmd === 2.U ){
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exReg_100M := localUpdate(15,8)
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} .elsewhen( spiCmd === 0.U ){
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exReg_100M := spiRegDown.io.datar
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}
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel =/= 0.U ){
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exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
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}
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when( isSckNegedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U & spiCmd === 3.U ){
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exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
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} .elsewhen( isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
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exMask_100M := Cat( exMask_100M(15,8), exReg_100M )
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}
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}
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}
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@@ -83,42 +116,28 @@ with BackBoardSpiSlv{
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val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B)
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when( isCrcPass ){
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localUpdate := localUpdate & ~( 1.U << downRegTemp(0)(3,0) )
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} .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 3.U ){
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localUpdate := localUpdate & (~exReg_100M(15,0))
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} .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) ){
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localUpdate := localUpdate & ~exMask_100M
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}
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spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & downCnt =/= 0.U
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spiRegDown.io.dataw := io.lvdsSlv.downstream_rx_data_out
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spiRegDown.io.addrw := Cat( downRegTemp(0)(3,0), downCnt(4,0))
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spiRegUp.io.enr := io.lvdsSlv.upstream_tx_data_ready
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spiRegUp.io.addrr := Cat( statusPage, upCnt(4,0)+1.U )
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io.lvdsSlv.upstream_tx_data_in :=
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Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
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// for( i <- 0 until page ){
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when( isCrcPass ){
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localReg.io.addrw := downRegTemp(0)(3,0)
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localReg.io.enw := true.B
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localReg.io.dataw := Cat( (1 until 32).map{ i => downRegTemp(i) }.reverse )
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} .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 1.U ){
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localReg.io.addrw := pageSel
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localReg.io.enw := true.B
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localReg.io.dataw := exReg_100M
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} .otherwise{
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localReg.io.addrw := DontCare
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localReg.io.enw := false.B
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localReg.io.dataw := DontCare
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}
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for( i <- 0 until 31 ) {
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upReg(i+1) := localReg.io.datar((30-i)*8+7, (30-i)*8)
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}
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}
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