ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

spi面积通过

Browse Source
This commit is contained in:
RuigeLee
2024-06-28 18:39:35 +08:00
parent b696723e23
commit e0bfd59539
2 changed files with 148 additions and 192 deletions
Download Patch File Download Diff File Expand all files Collapse all files

227
src/main/scala/backBoard/MirrorSRAM.scala
View File

@@ -4,124 +4,6 @@ import chisel3._
import chisel3.util._
// class MirrorSRAM(dw: Int, cl: Int) extends RawModule {
// def line_w = log2Ceil(cl)
// val io = IO(new Bundle{
// val addrr = Input(UInt(line_w.W))
// val addrw = Input(UInt(line_w.W))
// val dataw = Input( UInt(dw.W) )
// val datar = Output( UInt(dw.W) )
// val enw = Input(Bool())
// val enr = Input(Bool())
// val clock = Input(Bool())
// val reset = Input(Bool())
// })
// withClockAndReset( io.clock.asClock, io.reset ){
// val mem = SyncReadMem( cl, UInt(dw.W) )
// io.datar := DontCare
// when( io.enr ) {
// io.datar := mem.read( io.addrr )
// }
// when( io.enw ) {
// mem.write( io.addrw, io.dataw )
// }
// }
// }
// val addrr = Input(UInt(line_w.W))
// val addrw = Input(UInt(line_w.W))
// val dataw = Input( UInt(dw.W) )
// val datar = Output( UInt(dw.W) )
// val enw = Input(Bool())
// val enr = Input(Bool())
// val clock = Input(Bool())
// val reset = Input(Bool())
// class MirrorSRAM(dw: Int, cl: Int) extends BlackBox with HasBlackBoxInline {
// require(dw == 8)
// require(cl == 2048)
// class MirrorSRAMIO extends Bundle{
// val addrr = Input(UInt(11.W))
// val addrw = Input(UInt(11.W))
// val dataw = Input( UInt(8.W) )
// val datar = Output( UInt(8.W) )
// val enw = Input(Bool())
// val enr = Input(Bool())
// val clockr = Input(Bool())
// val clockw = Input(Bool())
// }
// val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
// setInline("MirrorSRAM.v",
// """
// | module MirrorSRAM(
// | input [7:0] dataw,
// | input [10:0] addrw,
// | input enw,
// |
// | output [7:0] datar,
// | input [10:0] addrr,
// | input enr,
// |
// | input clockr,
// | input clockw
// | );
// |
// | reg [7:0] ram[0:2047];
// | reg [7:0] data_r_reg;
// |
// | always @(posedge clockw) begin
// | if(enw) begin
// | ram[addrw] <= #1 dataw;
// | end
// | end
// |
// | always @(posedge clockr) begin
// | if(enr) begin
// | data_r_reg <= #1 ram[addrr];
// | end
// | end
// |
// | assign datar = data_r_reg;
// |
// | initial begin
// | for ( integer i = 0; i < 2048; i = i + 1 ) begin
// | ram[i] = $random;
// | end
// |
// | data_r_reg = $random;
// | end
// |
// |endmodule
// """.stripMargin)
// }
class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDownIO extends Bundle{
@@ -337,13 +219,15 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
class MirrorSRAMSpi() extends BlackBox with HasBlackBoxInline {
class MirrorSRAMSpiIO extends Bundle{
val addrr = Input(UInt(4.W))
val addrw = Input(UInt(4.W))
val dataw = Input( UInt(248.W) )
val datar = Output( UInt(248.W) )
class SpiSRAMDown() extends BlackBox with HasBlackBoxInline {
class SpiSRAMDownIO extends Bundle{
val addrr = Input(UInt(9.W))
val addrw = Input(UInt(9.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
@@ -351,39 +235,92 @@ class MirrorSRAMSpi() extends BlackBox with HasBlackBoxInline {
val clockw = Input(Bool())
}
val io: MirrorSRAMSpiIO = IO(new MirrorSRAMSpiIO)
val io: SpiSRAMDownIO = IO(new SpiSRAMDownIO)
setInline("MirrorSRAMSpi.v",
setInline("SpiSRAMDown.v",
"""
| module MirrorSRAMSpi(
| input [3:0] addrr,
| input [3:0] addrw,
|
| input [247:0] dataw,
| output [247:0] datar,
| module SpiSRAMDown(
| input [7:0] dataw,
| input [8:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [8:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| input clockw
| );
|
| reg [247:0] ram[0:15];
| reg [247:0] data_r_reg;
| reg [7:0] ram[0:511];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| end
| end
|
| assign datar = data_r_reg;
|
|
|endmodule
""".stripMargin)
}
class SpiSRAMUp extends BlackBox with HasBlackBoxInline {
class SpiSRAMUpIO extends Bundle{
val addrr = Input(UInt(9.W))
val addrw = Input(UInt(9.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
val clockr = Input(Bool())
val clockw = Input(Bool())
}
val io: SpiSRAMUpIO = IO(new SpiSRAMUpIO)
setInline("SpiSRAMUp.v",
"""
| module SpiSRAMUp(
| input [7:0] dataw,
| input [8:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [8:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [7:0] ram[0:511];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| end
| end
|
| assign datar = data_r_reg;
|