spi已经加入，操作必要寄存器已加入，编译通过，未开始测试

src/main/scala/backBoard/shin/Interface.scala

@@ -13,7 +13,7 @@ class CommonRegisterBundle extends Bundle{
 
   // val isSoftReset  = Bool()
   val encryptKey   = UInt(128.W)
-  val isEncrypt    = Bool()
+  // val isEncrypt    = Bool()
 
   // val upRecErrorCnt   = UInt(32.W)
   // val downRecErrorCnt = UInt(32.W)
@@ -30,9 +30,9 @@ class CommonRegisterBundle extends Bundle{
   // val wdtOverflow = UInt(8.W)
 
   val timeStamp = UInt(64.W)
-  val deltaTime = UInt(32.W)
+  // val deltaTime = UInt(32.W)
 
-  val linkStatus = UInt(8.W)
+  // val linkStatus = UInt(8.W)
 
 
   val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
@@ -46,46 +46,48 @@ class MasterRegisterBundle extends Bundle{
 
 
   val txSM         = UInt(2.W)
-  val txStatus     = UInt(16.W)
+  val rxSM         = UInt(2.W)
+  val txLength     = UInt(12.W)
+  // val txStatus     = UInt(16.W)
 
 
-  val intEnable    = UInt(8.W)
+  // val intEnable    = UInt(8.W)
-  val intMask      = UInt(8.W)
+  // val intMask      = UInt(8.W)
-  val intStatus    = UInt(8.W)
+  // val intStatus    = UInt(8.W)
 
 }
 
 
 class SlaveRegisterBundle extends Bundle{
 
-  val RAMSize   = UInt(8.W)
+  // val RAMSize   = UInt(8.W)
-  val MMUNum    = UInt(8.W)
+  // val MMUNum    = UInt(8.W)
 
-  val nodeSeqAddr = UInt(16.W)
+  // val nodeSeqAddr = UInt(16.W)
-  val nodeSetAddr = UInt(16.W)
+  // val nodeSetAddr = UInt(16.W)
 
 
-  val ebmmu = Vec(8, new Bundle{
+  // val ebmmu = Vec(8, new Bundle{
-    val logicAddr = UInt(32.W)
+  //   val logicAddr = UInt(32.W)
-    val length = UInt(16.W)
+  //   val length = UInt(16.W)
-    val phyAddr = UInt(32.W)
+  //   val phyAddr = UInt(32.W)
-    val op = UInt(2.W)
+  //   val op = UInt(2.W)
-    val enable = Bool()
+  //   val enable = Bool()
-  })
+  // })
 
-  val intStatus = UInt(16.W)
+  // val intStatus = UInt(16.W)
-  val mb = Vec(8, new Bundle{
+  // val mb = Vec(8, new Bundle{
-    val ctrl = UInt(8.W)
+  //   val ctrl = UInt(8.W)
-    val status = UInt(8.W)
+  //   val status = UInt(8.W)
-  })
+  // })
 
 
-  val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器 
+  // val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器 
-  val upTimeStamp   = UInt(64.W) //上行本地时间戳寄存器
+  // val upTimeStamp   = UInt(64.W) //上行本地时间戳寄存器
-  val mstTimeStamp  = UInt(64.W) //主站时间戳
+  // val mstTimeStamp  = UInt(64.W) //主站时间戳
 
-  val dcSyncEnable = Bool()
+  // val dcSyncEnable = Bool()
-  val dcSyncWidth  = UInt(16.W)
+  // val dcSyncWidth  = UInt(16.W)
 }
 
 
@@ -93,21 +95,15 @@ class SlaveRegisterBundle extends Bundle{
 class InterfaceIO extends Bundle{
   val ospi = new SPIInterfaceIO
 
-  // val req = Valid(new Bundle{
-  //   val addr = UInt(16.W)
-  //   val dataw = UInt(8.W)
-  //   val isWRn = Bool()
-  // })
 
-  // val resp = Valid(new Bundle{
+
-  //   datar = UInt(8.W)
-  // })
 
   val modeSel = Output(Bool())
 
   val txReq = Valid(new Bundle{
     val txSM = UInt(2.W)
     val rxSM = UInt(2.W)
+    val txLength = UInt(12.W)
   }) //发送请求和SM代号
 
 
@@ -117,7 +113,10 @@ class InterfaceIO extends Bundle{
   val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
   val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI
 
+  val timeStamp = Output(UInt(64.W))
 
+  val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
+  val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
 }
 
 
@@ -129,9 +128,11 @@ abstract class InterfaceBase extends Module{
 
   val cReg = Wire(new CommonRegisterBundle)
   val mReg = Wire(new MasterRegisterBundle)
-  val sReg = Wire(new SlaveRegisterBundle)
+  // val sReg = Wire(new SlaveRegisterBundle)
 
   val isSysInit = cReg.mstOrSlv =/= 0.U
+  val isMstMode = cReg.mstOrSlv === "h1".U
+  val isSlvMode = cReg.mstOrSlv === "h2".U
 
   def AcquireReg(addr: UInt): UInt = {
     Mux1H(
@@ -141,16 +142,24 @@ abstract class InterfaceBase extends Module{
       ) ++
 
       ((0 until 6).map{ i =>
-        (addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0),
+        (addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0 )
       }) ++
       
       Seq(
-        (addr === "h8".U) -> cReg.busRate( 7,0),
+        (addr === "h8".U )  -> cReg.busRate( 7,0),
-        (addr === "h9".U) -> cReg.busRate(15,8),        
+        (addr === "h9".U )  -> cReg.busRate(15,8),
+
+        (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
+        (addr === "h21".U & isMstMode) -> mReg.txLength,
+
+
       ) ++
 
+
+
+
       ((0 until 16).map{ i =>
-        (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0),
+        (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
       }) ++
 
       Seq()
@@ -169,22 +178,20 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
 
 
-  oSpi.io.addrSel = Output(UInt(16.W))
+
-  oSpi.io.dataw   = Output( UInt(8.W) )
   oSpi.io.datar   :=
     MuxCase( 0.U, Array(
       ((oSpi.io.addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
-      ((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> smUnit(0).io.sram_r.datar,
+      ((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
       ((oSpi.io.addrSel & "hFF00".U) === "h1000".U) -> 0.U,
-      ((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> smUnit(2).io.sram_r.datar,
+      ((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
       ((oSpi.io.addrSel & "hFF00".U) === "h2000".U) -> 0.U,
-      ((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> smUnit(4).io.sram_r.datar,
+      ((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar,
       ((oSpi.io.addrSel & "hFF00".U) === "h3000".U) -> 0.U,
-      ((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> smUnit(6).io.sram_r.datar,
+      ((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar,
       ((oSpi.io.addrSel & "hFF00".U) === "h4000".U) -> 0.U,
     ))
 
-  oSpi.io.isEnW   = Output(Bool())
 
   val isEnW = oSpi.io.isEnW
   val addrSel = oSpi.io.addrSel
@@ -211,12 +218,14 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     Cat(
       (0 until 16).map{ i =>
         RegEnable( dataw, 0.U, isEnW & addrSel === ("h80".U + i.U) & cReg.mstOrSlv === 0.U )
-      }.reserve
+      }.reverse
     )
 
 
 
-
+  mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
+  mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
+  mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
 
 
 
@@ -232,6 +241,12 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 }
 
 trait InterfaceCheckSM{ this: InterfaceBase =>
+  val isEnW: Bool
+  val addrSel: UInt
+  val dataw: UInt
+  val isEnR: Bool
+
+
   mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
   mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
 
@@ -274,31 +289,43 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
   io.sram_w(2).enw   := isEnW & (( addrSel & "hF800".U ) === "h3000".U)
   io.sram_w(3).enw   := isEnW & (( addrSel & "hF800".U ) === "h4000".U)
 
-  io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(0))
+  io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(0))
-  io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(2))
+  io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(2))
-  io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(4))
+  io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(4))
-  io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(6))
+  io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(6))
 
-  io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === smEnqAddr(1))
+  io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smEnqAddr(1))
-  io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === smEnqAddr(3))
+  io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smEnqAddr(3))
-  io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === smEnqAddr(5))
+  io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smEnqAddr(5))
-  io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === smEnqAddr(7))
+  io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smEnqAddr(7))
 }
 
 trait InterfaceLVDSop{ this: InterfaceBase =>
 
 }
 
+trait InterfaceSync{ this: InterfaceBase =>
+  cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
+  io.timeStamp := cReg.timeStamp
 
+}
 
 class Interface extends InterfaceBase
 with InterfaceMCUop
+with InterfaceCheckSM
+with InterfaceLVDSop
+with InterfaceSync
 {
 
   io.modeSel := cReg.mstOrSlv === "h1".U
 
   io.txReq.bits.txSM  := mReg.txSM
   io.txReq.bits.rxSM  := mReg.rxSM
-  io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U
+  io.txReq.bits.txLength := mReg.txLength
+  io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U
+
+  io.smEnqAddr := cReg.smEnqAddr
+  io.smDeqAddr := cReg.smDeqAddr
+
 
 }

src/main/scala/backBoard/shin/MasterParser.scala

@@ -11,9 +11,7 @@ class MasterParserIO extends Bundle{
   val sram_r = Flipped(new SRAM2kRDIO)
 
   val req = Flipped(Valid(new Bundle{
-    val txAddr    = UInt(15.W)
+    val txLength  = UInt(12.W)
-    val rxAddr    = UInt(15.W)
-    val length  = UInt(12.W)
   }))
   val rsp = Valid(new Bundle{
     val isError = Bool()
@@ -23,8 +21,6 @@ class MasterParserIO extends Bundle{
   val rxEnq = Output( Bool())
   val txDeq  = Output( Bool())
 
-  // val trigAddr = Input( Vec(2, UInt(15.W)) )
-
   val timeStamp = Input(UInt(64.W))
 
 }
@@ -58,21 +54,21 @@ abstract class MasterParserBase extends Module{
   }
 
   when( io.req.fire ){
-    txLen  := io.req.bits.length
+    txLen  := io.req.bits.txLength
-    rxLen  := io.req.bits.length
+    rxLen  := io.req.bits.txLength
     txCnt  := 0.U
   } .elsewhen( io.downOut.fire ){
     txCnt := txCnt + 1.U
   }
 
   when( io.req.fire ){
-    txAddr := io.req.bits.txAddr
+    txAddr := 0.U
   } .elsewhen( io.downOut.fire ){
     txAddr := txAddr + 1.U
   }
 
   when( io.req.fire ){
-    rxAddr := io.req.bits.rxAddr
+    rxAddr := 0.U
   } .elsewhen( io.upIn.fire ){
     rxAddr := rxAddr + 1.U
   }
@@ -82,7 +78,7 @@ abstract class MasterParserBase extends Module{
   io.sram_r.enr := 
     io.req.fire | io.downOut.fire
 
-  io.sram_r.addrr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )
+  io.sram_r.addrr := Mux( io.req.fire, 0.U, txAddr + 1.U )
 
   io.downOut.valid := ~reqReady
   io.downOut.bits.tdata := Mux1H(Seq(

src/main/scala/backBoard/shin/ShinTop.scala

@@ -22,18 +22,18 @@ class ShinTopIO extends Bundle{
 	// val interrupt = Output(Bool())
 	// val ctrl      = Input(UInt(4.W))
 
-  val timeStamp = Input(UInt(64.W))
-
-  val modeSel = Input(Bool())
 
 
 
+  val ospi = new SPIInterfaceIO
+
+
+  // val req = Flipped(Valid(new Bundle{
+  //   val txAddr    = UInt(15.W)
+  //   val rxAddr    = UInt(15.W)
+  //   val length  = UInt(12.W)
+  // }))
 
-  val req = Flipped(Valid(new Bundle{
-    val txAddr    = UInt(15.W)
-    val rxAddr    = UInt(15.W)
-    val length  = UInt(12.W)
-  }))
   val rsp = Valid(new Bundle{
     val isError = Bool()
     val length  = UInt(12.W)
@@ -68,12 +68,12 @@ abstract class ShinTopBase extends Module{
   io.uDatOut := upCDROut.io.serDat
 
   //override
-  when( slaveParser.io.isLoop & io.modeSel === false.B){
+  when( slaveParser.io.isLoop & interface.io.modeSel === false.B){
     upCDRIn.io.serDat := downCDROut.io.serDat
     io.dDatOut := false.B
   }
 
-
+  io.ospi <> interface.io.ospi
 
 
   val sram = Seq(
@@ -215,12 +215,12 @@ abstract class ShinTopBase extends Module{
 
 trait ShinTopMaster{ this: ShinTopBase =>
 
-  when(io.modeSel === true.B ){
+  when( interface.io.modeSel === true.B ){
     masterParser.io.downOut <> downCDROut.io.axis
     masterParser.io.upIn    <> upCDRIn.io.axis
   }
 
-  when( io.modeSel === true.B ){
+  when( interface.io.modeSel === true.B ){
 
     when( interface.io.txReq.bits.rxSM === 0.U ){
       smUnit(0).io.sram_w := masterParser.io.sram_w
@@ -263,29 +263,27 @@ trait ShinTopMaster{ this: ShinTopBase =>
 
   }
 
-  masterParser.io.req := io.req
+  masterParser.io.req.valid         := interface.io.txReq.valid
+  masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
+
   io.rsp := masterParser.io.rsp
 
-  // masterParser.io.trigAddr(0) := "hff".U
+  masterParser.io.timeStamp := interface.io.timeStamp
-  // masterParser.io.trigAddr(1) := "hff".U
-
-  masterParser.io.timeStamp := io.timeStamp
 }
 
 
 trait ShinTopSlave{ this: ShinTopBase =>
 
-  when( io.modeSel === false.B ){
+  when( interface.io.modeSel === false.B ){
     slaveParser.io.downIn  <> downCDRIn.io.axis
     downCDROut.io.axis <> slaveParser.io.downOut
     slaveParser.io.upIn    <> upCDRIn.io.axis
     upCDROut.io.axis <> slaveParser.io.upOut
   }
 
-  slaveParser.io.timeStamp := io.timeStamp
+  slaveParser.io.timeStamp := interface.io.timeStamp
+
 
-  val smEnqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
-  val smDeqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
 
   slaveParser.io.trigAddr(0) := interface.io.smEnqAddr(0)
   slaveParser.io.trigAddr(1) := interface.io.smDeqAddr(1)
@@ -300,7 +298,7 @@ trait ShinTopSlave{ this: ShinTopBase =>
 
 
 
-  when( io.modeSel === false.B ){
+  when( interface.io.modeSel === false.B ){
     smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
     smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
     smUnit(4).io.sram_w := slaveParser.io.sram_w(2)