ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

spi已经加入，操作必要寄存器已加入，编译通过，未开始测试

Browse Source
This commit is contained in:
Ruige Lee
2025-05-09 17:44:54 +08:00
parent f05b61542c
commit e079103037
3 changed files with 112 additions and 91 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -22,18 +22,18 @@ class ShinTopIO extends Bundle{
// val interrupt = Output(Bool())
// val ctrl = Input(UInt(4.W))
val timeStamp = Input(UInt(64.W))
val modeSel = Input(Bool())
val ospi = new SPIInterfaceIO
// val req = Flipped(Valid(new Bundle{
// val txAddr = UInt(15.W)
// val rxAddr = UInt(15.W)
// val length = UInt(12.W)
// }))
val req = Flipped(Valid(new Bundle{
val txAddr = UInt(15.W)
val rxAddr = UInt(15.W)
val length = UInt(12.W)
}))
val rsp = Valid(new Bundle{
val isError = Bool()
val length = UInt(12.W)
@@ -68,12 +68,12 @@ abstract class ShinTopBase extends Module{
io.uDatOut := upCDROut.io.serDat
//override
when( slaveParser.io.isLoop & io.modeSel === false.B){
when( slaveParser.io.isLoop & interface.io.modeSel === false.B){
upCDRIn.io.serDat := downCDROut.io.serDat
io.dDatOut := false.B
}
io.ospi <> interface.io.ospi
val sram = Seq(
@@ -215,12 +215,12 @@ abstract class ShinTopBase extends Module{
trait ShinTopMaster{ this: ShinTopBase =>
when(io.modeSel === true.B ){
when( interface.io.modeSel === true.B ){
masterParser.io.downOut <> downCDROut.io.axis
masterParser.io.upIn <> upCDRIn.io.axis
}
when( io.modeSel === true.B ){
when( interface.io.modeSel === true.B ){
when( interface.io.txReq.bits.rxSM === 0.U ){
smUnit(0).io.sram_w := masterParser.io.sram_w
@@ -263,29 +263,27 @@ trait ShinTopMaster{ this: ShinTopBase =>
}
masterParser.io.req := io.req
masterParser.io.req.valid := interface.io.txReq.valid
masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
io.rsp := masterParser.io.rsp
// masterParser.io.trigAddr(0) := "hff".U
// masterParser.io.trigAddr(1) := "hff".U
masterParser.io.timeStamp := io.timeStamp
masterParser.io.timeStamp := interface.io.timeStamp
}
trait ShinTopSlave{ this: ShinTopBase =>
when( io.modeSel === false.B ){
when( interface.io.modeSel === false.B ){
slaveParser.io.downIn <> downCDRIn.io.axis
downCDROut.io.axis <> slaveParser.io.downOut
slaveParser.io.upIn <> upCDRIn.io.axis
upCDROut.io.axis <> slaveParser.io.upOut
}
slaveParser.io.timeStamp := io.timeStamp
slaveParser.io.timeStamp := interface.io.timeStamp
val smEnqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
val smDeqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
slaveParser.io.trigAddr(0) := interface.io.smEnqAddr(0)
slaveParser.io.trigAddr(1) := interface.io.smDeqAddr(1)
@@ -300,7 +298,7 @@ trait ShinTopSlave{ this: ShinTopBase =>
when( io.modeSel === false.B ){
when( interface.io.modeSel === false.B ){
smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
smUnit(4).io.sram_w := slaveParser.io.sram_w(2)