spi已经加入，操作必要寄存器已加入，编译通过，未开始测试

src/main/scala/backBoard/shin/MasterParser.scala

@@ -11,9 +11,7 @@ class MasterParserIO extends Bundle{
   val sram_r = Flipped(new SRAM2kRDIO)
 
   val req = Flipped(Valid(new Bundle{
-    val txAddr    = UInt(15.W)
-    val rxAddr    = UInt(15.W)
-    val length  = UInt(12.W)
+    val txLength  = UInt(12.W)
   }))
   val rsp = Valid(new Bundle{
     val isError = Bool()
@@ -23,8 +21,6 @@ class MasterParserIO extends Bundle{
   val rxEnq = Output( Bool())
   val txDeq  = Output( Bool())
 
-  // val trigAddr = Input( Vec(2, UInt(15.W)) )
-
   val timeStamp = Input(UInt(64.W))
 
 }
@@ -58,21 +54,21 @@ abstract class MasterParserBase extends Module{
   }
 
   when( io.req.fire ){
-    txLen  := io.req.bits.length
-    rxLen  := io.req.bits.length
+    txLen  := io.req.bits.txLength
+    rxLen  := io.req.bits.txLength
     txCnt  := 0.U
   } .elsewhen( io.downOut.fire ){
     txCnt := txCnt + 1.U
   }
 
   when( io.req.fire ){
-    txAddr := io.req.bits.txAddr
+    txAddr := 0.U
   } .elsewhen( io.downOut.fire ){
     txAddr := txAddr + 1.U
   }
 
   when( io.req.fire ){
-    rxAddr := io.req.bits.rxAddr
+    rxAddr := 0.U
   } .elsewhen( io.upIn.fire ){
     rxAddr := rxAddr + 1.U
   }
@@ -82,7 +78,7 @@ abstract class MasterParserBase extends Module{
   io.sram_r.enr := 
     io.req.fire | io.downOut.fire
 
-  io.sram_r.addrr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )
+  io.sram_r.addrr := Mux( io.req.fire, 0.U, txAddr + 1.U )
 
   io.downOut.valid := ~reqReady
   io.downOut.bits.tdata := Mux1H(Seq(