spi已经加入，操作必要寄存器已加入，编译通过，未开始测试
This commit is contained in:
Ruige Lee
@@ -13,7 +13,7 @@ class CommonRegisterBundle extends Bundle{
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// val isSoftReset = Bool()
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val encryptKey = UInt(128.W)
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val isEncrypt = Bool()
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// val isEncrypt = Bool()
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// val upRecErrorCnt = UInt(32.W)
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// val downRecErrorCnt = UInt(32.W)
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@@ -30,9 +30,9 @@ class CommonRegisterBundle extends Bundle{
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// val wdtOverflow = UInt(8.W)
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val timeStamp = UInt(64.W)
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val deltaTime = UInt(32.W)
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// val deltaTime = UInt(32.W)
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val linkStatus = UInt(8.W)
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// val linkStatus = UInt(8.W)
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val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
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@@ -46,46 +46,48 @@ class MasterRegisterBundle extends Bundle{
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val txSM = UInt(2.W)
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val txStatus = UInt(16.W)
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val rxSM = UInt(2.W)
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val txLength = UInt(12.W)
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// val txStatus = UInt(16.W)
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val intEnable = UInt(8.W)
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val intMask = UInt(8.W)
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val intStatus = UInt(8.W)
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// val intEnable = UInt(8.W)
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// val intMask = UInt(8.W)
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// val intStatus = UInt(8.W)
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}
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class SlaveRegisterBundle extends Bundle{
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val RAMSize = UInt(8.W)
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val MMUNum = UInt(8.W)
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// val RAMSize = UInt(8.W)
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// val MMUNum = UInt(8.W)
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val nodeSeqAddr = UInt(16.W)
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val nodeSetAddr = UInt(16.W)
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// val nodeSeqAddr = UInt(16.W)
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// val nodeSetAddr = UInt(16.W)
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val ebmmu = Vec(8, new Bundle{
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val logicAddr = UInt(32.W)
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val length = UInt(16.W)
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val phyAddr = UInt(32.W)
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val op = UInt(2.W)
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val enable = Bool()
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})
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// val ebmmu = Vec(8, new Bundle{
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// val logicAddr = UInt(32.W)
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// val length = UInt(16.W)
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// val phyAddr = UInt(32.W)
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// val op = UInt(2.W)
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// val enable = Bool()
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// })
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val intStatus = UInt(16.W)
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val mb = Vec(8, new Bundle{
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val ctrl = UInt(8.W)
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val status = UInt(8.W)
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})
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// val intStatus = UInt(16.W)
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// val mb = Vec(8, new Bundle{
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// val ctrl = UInt(8.W)
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// val status = UInt(8.W)
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// })
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val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器
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val upTimeStamp = UInt(64.W) //上行本地时间戳寄存器
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val mstTimeStamp = UInt(64.W) //主站时间戳
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// val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器
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// val upTimeStamp = UInt(64.W) //上行本地时间戳寄存器
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// val mstTimeStamp = UInt(64.W) //主站时间戳
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val dcSyncEnable = Bool()
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val dcSyncWidth = UInt(16.W)
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// val dcSyncEnable = Bool()
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// val dcSyncWidth = UInt(16.W)
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}
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@@ -93,21 +95,15 @@ class SlaveRegisterBundle extends Bundle{
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class InterfaceIO extends Bundle{
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val ospi = new SPIInterfaceIO
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// val req = Valid(new Bundle{
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// val addr = UInt(16.W)
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// val dataw = UInt(8.W)
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// val isWRn = Bool()
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// })
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// val resp = Valid(new Bundle{
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// datar = UInt(8.W)
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// })
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val modeSel = Output(Bool())
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val txReq = Valid(new Bundle{
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val txSM = UInt(2.W)
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val rxSM = UInt(2.W)
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val txLength = UInt(12.W)
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}) //发送请求和SM代号
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@@ -117,7 +113,10 @@ class InterfaceIO extends Bundle{
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val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
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val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI
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val timeStamp = Output(UInt(64.W))
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val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
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val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
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}
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@@ -129,9 +128,11 @@ abstract class InterfaceBase extends Module{
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val cReg = Wire(new CommonRegisterBundle)
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val mReg = Wire(new MasterRegisterBundle)
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val sReg = Wire(new SlaveRegisterBundle)
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// val sReg = Wire(new SlaveRegisterBundle)
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val isSysInit = cReg.mstOrSlv =/= 0.U
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val isMstMode = cReg.mstOrSlv === "h1".U
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val isSlvMode = cReg.mstOrSlv === "h2".U
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def AcquireReg(addr: UInt): UInt = {
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Mux1H(
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@@ -141,16 +142,24 @@ abstract class InterfaceBase extends Module{
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) ++
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((0 until 6).map{ i =>
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(addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0),
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(addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0 )
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}) ++
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Seq(
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(addr === "h8".U) -> cReg.busRate( 7,0),
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(addr === "h9".U) -> cReg.busRate(15,8),
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(addr === "h8".U ) -> cReg.busRate( 7,0),
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(addr === "h9".U ) -> cReg.busRate(15,8),
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(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
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(addr === "h21".U & isMstMode) -> mReg.txLength,
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) ++
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((0 until 16).map{ i =>
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(addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0),
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(addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
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}) ++
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Seq()
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@@ -169,22 +178,20 @@ trait InterfaceMCUop{ this: InterfaceBase =>
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oSpi.io.addrSel = Output(UInt(16.W))
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oSpi.io.dataw = Output( UInt(8.W) )
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oSpi.io.datar :=
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MuxCase( 0.U, Array(
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((oSpi.io.addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
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((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> smUnit(0).io.sram_r.datar,
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((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
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((oSpi.io.addrSel & "hFF00".U) === "h1000".U) -> 0.U,
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((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> smUnit(2).io.sram_r.datar,
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((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
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((oSpi.io.addrSel & "hFF00".U) === "h2000".U) -> 0.U,
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((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> smUnit(4).io.sram_r.datar,
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((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar,
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((oSpi.io.addrSel & "hFF00".U) === "h3000".U) -> 0.U,
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((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> smUnit(6).io.sram_r.datar,
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((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar,
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((oSpi.io.addrSel & "hFF00".U) === "h4000".U) -> 0.U,
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))
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oSpi.io.isEnW = Output(Bool())
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val isEnW = oSpi.io.isEnW
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val addrSel = oSpi.io.addrSel
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@@ -211,12 +218,14 @@ trait InterfaceMCUop{ this: InterfaceBase =>
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Cat(
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(0 until 16).map{ i =>
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RegEnable( dataw, 0.U, isEnW & addrSel === ("h80".U + i.U) & cReg.mstOrSlv === 0.U )
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}.reserve
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}.reverse
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)
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mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
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mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
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mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
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@@ -232,6 +241,12 @@ trait InterfaceMCUop{ this: InterfaceBase =>
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}
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trait InterfaceCheckSM{ this: InterfaceBase =>
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val isEnW: Bool
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val addrSel: UInt
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val dataw: UInt
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val isEnR: Bool
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mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
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mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
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@@ -274,31 +289,43 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
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io.sram_w(2).enw := isEnW & (( addrSel & "hF800".U ) === "h3000".U)
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io.sram_w(3).enw := isEnW & (( addrSel & "hF800".U ) === "h4000".U)
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io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(0))
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io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(2))
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io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(4))
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io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(6))
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io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(0))
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io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(2))
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io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(4))
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io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(6))
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io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === smEnqAddr(1))
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io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === smEnqAddr(3))
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io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === smEnqAddr(5))
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io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === smEnqAddr(7))
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io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smEnqAddr(1))
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io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smEnqAddr(3))
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io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smEnqAddr(5))
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io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smEnqAddr(7))
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}
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trait InterfaceLVDSop{ this: InterfaceBase =>
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}
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trait InterfaceSync{ this: InterfaceBase =>
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cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
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io.timeStamp := cReg.timeStamp
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}
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class Interface extends InterfaceBase
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with InterfaceMCUop
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with InterfaceCheckSM
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with InterfaceLVDSop
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with InterfaceSync
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{
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io.modeSel := cReg.mstOrSlv === "h1".U
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io.txReq.bits.txSM := mReg.txSM
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io.txReq.bits.rxSM := mReg.rxSM
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io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U
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io.txReq.bits.txLength := mReg.txLength
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io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U
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io.smEnqAddr := cReg.smEnqAddr
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io.smDeqAddr := cReg.smDeqAddr
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}
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