ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

总线mux的bug修复

Browse Source
This commit is contained in:
RuigeLee
2024-11-04 16:47:01 +08:00
parent 4a219df882
commit df175dc099
2 changed files with 19 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/backBoard/pico/BackSystem.scala
View File

@@ -155,8 +155,8 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) === "b1".U sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) === "b1".U
cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(10) === "b0".U & ~pico.io.mem.instr
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(10) === "b1".U & ~pico.io.mem.instr
pico.io.mem.ready := pico.io.mem.ready :=
Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready, Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready,

17
tb/sw/src/SlvMain.c
View File

@@ -64,7 +64,7 @@ void main()
readDat = *cdr_rxFifo; readDat = *cdr_rxFifo;
if( operator == 0 ){ if( operator == 0 ){
slvNum = 64 - ( downRecvLen >> 3 );
uint32_t localLen = 8; uint32_t localLen = 8;
uint32_t downSendLen = downRecvLen - 8; uint32_t downSendLen = downRecvLen - 8;
@@ -79,6 +79,8 @@ void main()
readDat = *cdr_rxFifo; readDat = *cdr_rxFifo;
} }
if(!isLast){ if(!isLast){
// 下行转发新建包头 // 下行转发新建包头
*cdr_txLen = downRecvLen; //downSendLen + 8 *cdr_txLen = downRecvLen; //downSendLen + 8
@@ -91,8 +93,8 @@ void main()
"andi ra, sp, 0x08\n" "andi ra, sp, 0x08\n"
"1:\n" "1:\n"
"bnez ra, 1b\n" //error 速度不够，不再检查接收 "bnez ra, 1b\n" //error 速度不够，不再检查接收
"lw t1, 0x01c(x0)\n" "lw t2, 0x01c(x0)\n"
"sw t1, 0x008(x0)\n" "sw t2, 0x008(x0)\n"
); );
//*cdr_0_tx_txFifo = *cdr_0_rx_rxFifo; //接收即发送 //*cdr_0_tx_txFifo = *cdr_0_rx_rxFifo; //接收即发送
} }
@@ -105,7 +107,7 @@ void main()
"1:\n" "1:\n"
"bnez ra, 1b\n" //error 速度不够，不再检查接收 "bnez ra, 1b\n" //error 速度不够，不再检查接收
// "lui t0, %hi(0x40000000)\n" // "lui t0, %hi(0x40000000)\n"
"lw t1, 0x01c(x0)\n" "lw t2, 0x01c(x0)\n"
); );
} }
} }
@@ -202,8 +204,8 @@ void main()
"andi ra, sp, 0x80\n" "andi ra, sp, 0x80\n"
"1:\n" "1:\n"
"bnez ra, 1b\n" //error 速度不够，不再检查接收 "bnez ra, 1b\n" //error 速度不够，不再检查接收
"lw t1, 0x01c(x0)\n" "lw t2, 0x01c(x0)\n"
"sw t1, 0x008(x0)\n" "sw t2, 0x008(x0)\n"
); );
// *cdr_1_tx_txFifo = *cdr_1_rx_rxFifo; //接收即发送 // *cdr_1_tx_txFifo = *cdr_1_rx_rxFifo; //接收即发送
@@ -247,7 +249,8 @@ void main()
"andi sp, sp, 0xFE\n" "andi sp, sp, 0xFE\n"
); );
slvNum = 64 - ( downRecvLen >> 3 );
*WriteGpio = 1 << slvNum;
} else if ( operator == 1 ){ } else if ( operator == 1 ){
error(); error();