ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

总线mux的bug修复

Browse Source
This commit is contained in:
RuigeLee
2024-11-04 16:47:01 +08:00
parent 4a219df882
commit df175dc099
2 changed files with 19 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/backBoard/pico/BackSystem.scala
View File

@@ -155,8 +155,8 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) === "b1".U
cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr
cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(10) === "b0".U & ~pico.io.mem.instr
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) =/= "b1".U & pico.io.mem.addr.extract(10) === "b1".U & ~pico.io.mem.instr
pico.io.mem.ready :=
Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready,