From df0eeeb956a63f9328444af76aaf676a1ed622ae Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 22 May 2025 19:44:25 +0800 Subject: [PATCH] =?UTF-8?q?=E5=8A=A0=E5=BC=BAlvds=E4=BE=A7sm=E5=88=87?= =?UTF-8?q?=E6=8D=A2=E7=9A=84=E6=9D=A1=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveParser.scala | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 4487a74..3e059d8 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -569,14 +569,14 @@ trait SlaveParserRW{ this: SlaveParserBase => io.sram_r(3).addrr := addrr(10,0) - io.dSMenq(0) := isWrite & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0) - io.uSMdeq(0) := isRead & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === addrr(10,0) - io.dSMenq(1) := isWrite & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0) - io.uSMdeq(1) := isRead & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === addrr(10,0) - io.dSMenq(2) := isWrite & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0) - io.uSMdeq(2) := isRead & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === addrr(10,0) - io.dSMenq(3) := isWrite & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0) - io.uSMdeq(3) := isRead & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === addrr(10,0) + io.dSMenq(0) := io.sram_w(0).enw & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0) + io.uSMdeq(0) := isLvdsEnR & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === addrr(10,0) + io.dSMenq(1) := io.sram_w(1).enw & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0) + io.uSMdeq(1) := isLvdsEnR & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === addrr(10,0) + io.dSMenq(2) := io.sram_w(2).enw & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0) + io.uSMdeq(2) := isLvdsEnR & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === addrr(10,0) + io.dSMenq(3) := io.sram_w(3).enw & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0) + io.uSMdeq(3) := isLvdsEnR & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === addrr(10,0) }