diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 4487a74..3e059d8 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -569,14 +569,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   io.sram_r(3).addrr := addrr(10,0)
 
 
-  io.dSMenq(0) := isWrite & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0)
-  io.uSMdeq(0) := isRead  & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === addrr(10,0)
-  io.dSMenq(1) := isWrite & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0)
-  io.uSMdeq(1) := isRead  & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === addrr(10,0)
-  io.dSMenq(2) := isWrite & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0)
-  io.uSMdeq(2) := isRead  & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === addrr(10,0)
-  io.dSMenq(3) := isWrite & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0)
-  io.uSMdeq(3) := isRead  & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === addrr(10,0)
+  io.dSMenq(0) := io.sram_w(0).enw & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0)
+  io.uSMdeq(0) := isLvdsEnR  & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === addrr(10,0)
+  io.dSMenq(1) := io.sram_w(1).enw & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0)
+  io.uSMdeq(1) := isLvdsEnR  & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === addrr(10,0)
+  io.dSMenq(2) := io.sram_w(2).enw & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0)
+  io.uSMdeq(2) := isLvdsEnR  & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === addrr(10,0)
+  io.dSMenq(3) := io.sram_w(3).enw & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0)
+  io.uSMdeq(3) := isLvdsEnR  & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === addrr(10,0)
 
 
 }