ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

sim env

Browse Source
This commit is contained in:
RuigeLee
2023-07-17 09:26:20 +08:00
parent 25584bf6f5
commit de5eb461f6
25 changed files with 4016 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

431
tb/vtb/SimTop.v Normal file
View File

@@ -0,0 +1,431 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module SimTop (
output success,
output fail,
input CLK,
input RSTn
);
wire mem_axi4_0_aw_ready;
wire mem_axi4_0_aw_valid;
wire [3:0] mem_axi4_0_aw_bits_id;
wire [31:0] mem_axi4_0_aw_bits_addr;
wire [7:0] mem_axi4_0_aw_bits_len;
wire [2:0] mem_axi4_0_aw_bits_size;
wire [1:0] mem_axi4_0_aw_bits_burst;
wire mem_axi4_0_aw_bits_lock;
wire [3:0] mem_axi4_0_aw_bits_cache;
wire [2:0] mem_axi4_0_aw_bits_prot;
wire [3:0] mem_axi4_0_aw_bits_qos;
wire mem_axi4_0_w_ready;
wire mem_axi4_0_w_valid;
wire [31:0] mem_axi4_0_w_bits_data;
wire [3:0] mem_axi4_0_w_bits_strb;
wire mem_axi4_0_w_bits_last;
wire mem_axi4_0_b_ready;
wire mem_axi4_0_b_valid;
wire [3:0] mem_axi4_0_b_bits_id;
wire [1:0] mem_axi4_0_b_bits_resp;
wire mem_axi4_0_ar_ready;
wire mem_axi4_0_ar_valid;
wire [3:0] mem_axi4_0_ar_bits_id;
wire [31:0] mem_axi4_0_ar_bits_addr;
wire [7:0] mem_axi4_0_ar_bits_len;
wire [2:0] mem_axi4_0_ar_bits_size;
wire [1:0] mem_axi4_0_ar_bits_burst;
wire mem_axi4_0_ar_bits_lock;
wire [3:0] mem_axi4_0_ar_bits_cache;
wire [2:0] mem_axi4_0_ar_bits_prot;
wire [3:0] mem_axi4_0_ar_bits_qos;
wire mem_axi4_0_r_ready;
wire mem_axi4_0_r_valid;
wire [3:0] mem_axi4_0_r_bits_id;
wire [31:0] mem_axi4_0_r_bits_data;
wire [1:0] mem_axi4_0_r_bits_resp;
wire mem_axi4_0_r_bits_last;
wire mmio_axi4_0_aw_ready;
wire mmio_axi4_0_aw_valid;
wire [3:0] mmio_axi4_0_aw_bits_id;
wire [30:0] mmio_axi4_0_aw_bits_addr;
wire [7:0] mmio_axi4_0_aw_bits_len;
wire [2:0] mmio_axi4_0_aw_bits_size;
wire [1:0] mmio_axi4_0_aw_bits_burst;
wire mmio_axi4_0_aw_bits_lock;
wire [3:0] mmio_axi4_0_aw_bits_cache;
wire [2:0] mmio_axi4_0_aw_bits_prot;
wire [3:0] mmio_axi4_0_aw_bits_qos;
wire mmio_axi4_0_w_ready;
wire mmio_axi4_0_w_valid;
wire [31:0] mmio_axi4_0_w_bits_data;
wire [3:0] mmio_axi4_0_w_bits_strb;
wire mmio_axi4_0_w_bits_last;
wire mmio_axi4_0_b_ready;
wire mmio_axi4_0_b_valid;
wire [3:0] mmio_axi4_0_b_bits_id;
wire [1:0] mmio_axi4_0_b_bits_resp;
wire mmio_axi4_0_ar_ready;
wire mmio_axi4_0_ar_valid;
wire [3:0] mmio_axi4_0_ar_bits_id;
wire [30:0] mmio_axi4_0_ar_bits_addr;
wire [7:0] mmio_axi4_0_ar_bits_len;
wire [2:0] mmio_axi4_0_ar_bits_size;
wire [1:0] mmio_axi4_0_ar_bits_burst;
wire mmio_axi4_0_ar_bits_lock;
wire [3:0] mmio_axi4_0_ar_bits_cache;
wire [2:0] mmio_axi4_0_ar_bits_prot;
wire [3:0] mmio_axi4_0_ar_bits_qos;
wire mmio_axi4_0_r_ready;
wire mmio_axi4_0_r_valid;
wire [3:0] mmio_axi4_0_r_bits_id;
wire [31:0] mmio_axi4_0_r_bits_data;
wire [1:0] mmio_axi4_0_r_bits_resp;
wire mmio_axi4_0_r_bits_last;
wire Mdi_I;
wire Mdc_O;
wire Mdo_O;
wire Mdo_OE;
wire mtx_clk;
wire [3:0] MTxD;
wire MTxEn;
wire MTxErr;
wire mrx_clk;
wire [3:0] MRxD;
wire MRxDV;
wire MRxErr;
wire MColl;
wire MCrs;
wire Mdio_IO;
assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz;
assign Mdi_I = Mdio_IO;
wire dmactive;
ExampleRocketSystem i_rocket(
.clock(CLK),
.reset(~RSTn),
.resetctrl_hartIsInReset_0(~RSTn),
.debug_clock(CLK),
.debug_reset(~RSTn),
.debug_systemjtag_jtag_TCK(1'b0),
.debug_systemjtag_jtag_TMS(1'b0),
.debug_systemjtag_jtag_TDI(1'b0),
.debug_systemjtag_jtag_TDO_data(),
.debug_systemjtag_jtag_TDO_driven(),
.debug_systemjtag_reset(~RSTn),
.debug_systemjtag_mfr_id(11'b0),
.debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0),
.debug_ndreset(),
.debug_dmactive(dmactive),
.debug_dmactiveAck(dmactive),
.mem_axi4_0_aw_ready (mem_axi4_0_aw_ready),
.mem_axi4_0_aw_valid (mem_axi4_0_aw_valid),
.mem_axi4_0_aw_bits_id (mem_axi4_0_aw_bits_id),
.mem_axi4_0_aw_bits_addr (mem_axi4_0_aw_bits_addr),
.mem_axi4_0_aw_bits_len (mem_axi4_0_aw_bits_len),
.mem_axi4_0_aw_bits_size (mem_axi4_0_aw_bits_size),
.mem_axi4_0_aw_bits_burst(mem_axi4_0_aw_bits_burst),
.mem_axi4_0_aw_bits_lock (mem_axi4_0_aw_bits_lock),
.mem_axi4_0_aw_bits_cache(mem_axi4_0_aw_bits_cache),
.mem_axi4_0_aw_bits_prot (mem_axi4_0_aw_bits_prot),
.mem_axi4_0_aw_bits_qos (mem_axi4_0_aw_bits_qos),
.mem_axi4_0_w_ready (mem_axi4_0_w_ready),
.mem_axi4_0_w_valid (mem_axi4_0_w_valid),
.mem_axi4_0_w_bits_data (mem_axi4_0_w_bits_data),
.mem_axi4_0_w_bits_strb (mem_axi4_0_w_bits_strb),
.mem_axi4_0_w_bits_last (mem_axi4_0_w_bits_last),
.mem_axi4_0_b_ready (mem_axi4_0_b_ready),
.mem_axi4_0_b_valid (mem_axi4_0_b_valid),
.mem_axi4_0_b_bits_id (mem_axi4_0_b_bits_id),
.mem_axi4_0_b_bits_resp (mem_axi4_0_b_bits_resp),
.mem_axi4_0_ar_ready (mem_axi4_0_ar_ready),
.mem_axi4_0_ar_valid (mem_axi4_0_ar_valid),
.mem_axi4_0_ar_bits_id (mem_axi4_0_ar_bits_id),
.mem_axi4_0_ar_bits_addr (mem_axi4_0_ar_bits_addr),
.mem_axi4_0_ar_bits_len (mem_axi4_0_ar_bits_len),
.mem_axi4_0_ar_bits_size (mem_axi4_0_ar_bits_size),
.mem_axi4_0_ar_bits_burst(mem_axi4_0_ar_bits_burst),
.mem_axi4_0_ar_bits_lock (mem_axi4_0_ar_bits_lock),
.mem_axi4_0_ar_bits_cache(mem_axi4_0_ar_bits_cache),
.mem_axi4_0_ar_bits_prot (mem_axi4_0_ar_bits_prot),
.mem_axi4_0_ar_bits_qos (mem_axi4_0_ar_bits_qos),
.mem_axi4_0_r_ready (mem_axi4_0_r_ready),
.mem_axi4_0_r_valid (mem_axi4_0_r_valid),
.mem_axi4_0_r_bits_id (mem_axi4_0_r_bits_id),
.mem_axi4_0_r_bits_data (mem_axi4_0_r_bits_data),
.mem_axi4_0_r_bits_resp (mem_axi4_0_r_bits_resp),
.mem_axi4_0_r_bits_last (mem_axi4_0_r_bits_last),
.mmio_axi4_0_aw_ready (mmio_axi4_0_aw_ready),
.mmio_axi4_0_aw_valid (mmio_axi4_0_aw_valid),
.mmio_axi4_0_aw_bits_id (mmio_axi4_0_aw_bits_id),
.mmio_axi4_0_aw_bits_addr (mmio_axi4_0_aw_bits_addr),
.mmio_axi4_0_aw_bits_len (mmio_axi4_0_aw_bits_len),
.mmio_axi4_0_aw_bits_size (mmio_axi4_0_aw_bits_size),
.mmio_axi4_0_aw_bits_burst(mmio_axi4_0_aw_bits_burst),
.mmio_axi4_0_aw_bits_lock (mmio_axi4_0_aw_bits_lock),
.mmio_axi4_0_aw_bits_cache(mmio_axi4_0_aw_bits_cache),
.mmio_axi4_0_aw_bits_prot (mmio_axi4_0_aw_bits_prot),
.mmio_axi4_0_aw_bits_qos (mmio_axi4_0_aw_bits_qos),
.mmio_axi4_0_w_ready (mmio_axi4_0_w_ready),
.mmio_axi4_0_w_valid (mmio_axi4_0_w_valid),
.mmio_axi4_0_w_bits_data (mmio_axi4_0_w_bits_data),
.mmio_axi4_0_w_bits_strb (mmio_axi4_0_w_bits_strb),
.mmio_axi4_0_w_bits_last (mmio_axi4_0_w_bits_last),
.mmio_axi4_0_b_ready (mmio_axi4_0_b_ready),
.mmio_axi4_0_b_valid (mmio_axi4_0_b_valid),
.mmio_axi4_0_b_bits_id (mmio_axi4_0_b_bits_id),
.mmio_axi4_0_b_bits_resp (mmio_axi4_0_b_bits_resp),
.mmio_axi4_0_ar_ready (mmio_axi4_0_ar_ready),
.mmio_axi4_0_ar_valid (mmio_axi4_0_ar_valid),
.mmio_axi4_0_ar_bits_id (mmio_axi4_0_ar_bits_id),
.mmio_axi4_0_ar_bits_addr (mmio_axi4_0_ar_bits_addr),
.mmio_axi4_0_ar_bits_len (mmio_axi4_0_ar_bits_len),
.mmio_axi4_0_ar_bits_size (mmio_axi4_0_ar_bits_size),
.mmio_axi4_0_ar_bits_burst(mmio_axi4_0_ar_bits_burst),
.mmio_axi4_0_ar_bits_lock (mmio_axi4_0_ar_bits_lock),
.mmio_axi4_0_ar_bits_cache(mmio_axi4_0_ar_bits_cache),
.mmio_axi4_0_ar_bits_prot (mmio_axi4_0_ar_bits_prot),
.mmio_axi4_0_ar_bits_qos (mmio_axi4_0_ar_bits_qos),
.mmio_axi4_0_r_ready (mmio_axi4_0_r_ready),
.mmio_axi4_0_r_valid (mmio_axi4_0_r_valid),
.mmio_axi4_0_r_bits_id (mmio_axi4_0_r_bits_id),
.mmio_axi4_0_r_bits_data (mmio_axi4_0_r_bits_data),
.mmio_axi4_0_r_bits_resp (mmio_axi4_0_r_bits_resp),
.mmio_axi4_0_r_bits_last (mmio_axi4_0_r_bits_last),
.interrupts(2'b0),
.macIO_mdi(Mdi_I),
.macIO_mdc(Mdc_O),
.macIO_mdo(Mdo_O),
.macIO_mdoEn(Mdo_OE),
.macIO_mtx_clk_pad_i(mtx_clk),
.macIO_mtxd_pad_o(MTxD),
.macIO_mtxen_pad_o(MTxEn),
.macIO_mtxerr_pad_o(MTxErr),
.macIO_mrx_clk_pad_i(mrx_clk),
.macIO_mrxd_pad_i(MRxD),
.macIO_mrxdv_pad_i(MRxDV),
.macIO_mrxerr_pad_i(MRxErr),
.macIO_mcoll_pad_i(MColl),
.macIO_mcrs_pad_i(MCrs)
);
integer phy_log_file_desc;
// eth_phy s_phy// This PHY model simulate simplified Intel LXT971A PHY
// (
// .m_rst_n_i(RSTn),
// .mtx_clk_o(mtx_clk),
// .mtxd_i(MTxD),
// .mtxen_i(MTxEn),
// .mtxerr_i(MTxErr),
// .mrx_clk_o(mrx_clk),
// .mrxd_o(MRxD),
// .mrxdv_o(MRxDV),
// .mrxerr_o(MRxErr),
// .mcoll_o(MColl),
// .mcrs_o(MCrs),
// .mdc_i(Mdc_O),
// .md_io(Mdio_IO),
// // SYSTEM
// .phy_log(phy_log_file_desc)
// );
// initial
// begin
// phy_log_file_desc = $fopen("./log/eth_tb_phy.log");
// $display(phy_log_file_desc, "================ PHY Module Testbench access log ================");
// $display(phy_log_file_desc, " ");
// end
axi_full_slv_sram # ( .DW(32), .AW(18) ) s_axi_full_slv_sram
(
.MEM_AWID (mem_axi4_0_aw_bits_id),
.MEM_BID (mem_axi4_0_b_bits_id),
.MEM_ARID (mem_axi4_0_ar_bits_id),
.MEM_RID (mem_axi4_0_r_bits_id),
.MEM_AWADDR (mem_axi4_0_aw_bits_addr),
.MEM_AWLEN (mem_axi4_0_aw_bits_len),
.MEM_AWSIZE (mem_axi4_0_aw_bits_size),
.MEM_AWBURST(mem_axi4_0_aw_bits_burst),
.MEM_AWVALID(mem_axi4_0_aw_valid),
.MEM_AWREADY(mem_axi4_0_aw_ready),
.MEM_WDATA (mem_axi4_0_w_bits_data),
.MEM_WSTRB (mem_axi4_0_w_bits_strb),
.MEM_WLAST (mem_axi4_0_w_bits_last),
.MEM_WVALID (mem_axi4_0_w_valid),
.MEM_WREADY (mem_axi4_0_w_ready),
.MEM_BRESP (mem_axi4_0_b_bits_resp),
.MEM_BVALID (mem_axi4_0_b_valid),
.MEM_BREADY (mem_axi4_0_b_ready),
.MEM_ARADDR (mem_axi4_0_ar_bits_addr),
.MEM_ARLEN (mem_axi4_0_ar_bits_len),
.MEM_ARSIZE (mem_axi4_0_ar_bits_size),
.MEM_ARBURST(mem_axi4_0_ar_bits_burst),
.MEM_ARVALID(mem_axi4_0_ar_valid),
.MEM_ARREADY(mem_axi4_0_ar_ready),
.MEM_RDATA (mem_axi4_0_r_bits_data),
.MEM_RRESP (mem_axi4_0_r_bits_resp),
.MEM_RLAST (mem_axi4_0_r_bits_last),
.MEM_RVALID (mem_axi4_0_r_valid),
.MEM_RREADY (mem_axi4_0_r_ready),
.CLK (CLK),
.RSTn (RSTn)
);
wire debugger_success;
debuger i_debuger(
.success(debugger_success),
.DEBUGER_AWID (mmio_axi4_0_aw_bits_id),
.DEBUGER_BID (mmio_axi4_0_b_bits_id),
.DEBUGER_ARID (mmio_axi4_0_ar_bits_id),
.DEBUGER_RID (mmio_axi4_0_r_bits_id),
.DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr),
.DEBUGER_AWVALID(mmio_axi4_0_aw_valid),
.DEBUGER_AWREADY(mmio_axi4_0_aw_ready),
.DEBUGER_WDATA (mmio_axi4_0_w_bits_data),
.DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb),
.DEBUGER_WVALID(mmio_axi4_0_w_valid),
.DEBUGER_WREADY(mmio_axi4_0_w_ready),
.DEBUGER_BRESP (mmio_axi4_0_b_bits_rsp),
.DEBUGER_BVALID(mmio_axi4_0_b_valid),
.DEBUGER_BREADY(mmio_axi4_0_b_ready),
.DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr),
.DEBUGER_ARVALID(mmio_axi4_0_ar_valid),
.DEBUGER_ARREADY(mmio_axi4_0_ar_ready),
.DEBUGER_RDATA (mmio_axi4_0_r_bits_data),
.DEBUGER_RRESP (mmio_axi4_0_r_bits_rsp),
.DEBUGER_RVALID(mmio_axi4_0_r_valid),
.DEBUGER_RREADY(mmio_axi4_0_r_ready),
.CLK(CLK),
.RSTn(RSTn)
);
assign success = debugger_success;
string testName;
`define MEM s_axi_full_slv_sram.i_sram.ram
reg [7:0] mem [0:200000];
localparam DP = 2**18;
integer i, by;
initial begin
#20
if ( $value$plusargs("%s",testName) ) begin
$display("%s",testName);
$readmemh(testName, mem);
end
else begin
$display("%s",testName);
$error("Failed to read Files!");
end
for ( i = 0; i < DP; i = i + 1 ) begin
for ( by = 0; by < 4; by = by + 1 ) begin
if ( | mem[i*4+by] ) begin
`MEM[i][8*by +: 8] = mem[i*4+by];
end
else begin
`MEM[i][8*by +: 8] = 8'h0;
end
end
end
$display("%x",`MEM[0]);
$display("%x",`MEM[1]);
$display("%x",`MEM[2]);
$display("%x",`MEM[3]);
end
endmodule

291
tb/vtb/axi_full_slv_sram.v Normal file
View File

@@ -0,0 +1,291 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module axi_full_slv_sram #
(
parameter DW = 32,
parameter AW = 14
)
(
input [3:0] MEM_AWID,
output [3:0] MEM_BID,
input [3:0] MEM_ARID,
output [3:0] MEM_RID,
input [31:0] MEM_AWADDR,
input [7:0] MEM_AWLEN,
input [2:0] MEM_AWSIZE,
input [1:0] MEM_AWBURST,
input MEM_AWVALID,
output MEM_AWREADY,
input [DW-1:0] MEM_WDATA,
input [DW/8-1:0] MEM_WSTRB,
input MEM_WLAST,
input MEM_WVALID,
output MEM_WREADY,
output [1:0] MEM_BRESP,
output MEM_BVALID,
input MEM_BREADY,
input [31:0] MEM_ARADDR,
input [7:0] MEM_ARLEN,
input [2:0] MEM_ARSIZE,
input [1:0] MEM_ARBURST,
input MEM_ARVALID,
output MEM_ARREADY,
output [DW-1:0] MEM_RDATA,
output [1:0] MEM_RRESP,
output MEM_RLAST,
output MEM_RVALID,
input MEM_RREADY,
input CLK,
input RSTn
);
localparam ADDR_LSB = $clog2(DW/8);
gen_dffren # (.DW(4)) awid_dffren (.dnxt(MEM_AWID), .qout(MEM_BID), .en(MEM_AWVALID & MEM_AWREADY), .CLK(CLK), .RSTn(RSTn));
gen_dffren # (.DW(4)) arid_dffren (.dnxt(MEM_ARID), .qout(MEM_RID), .en(MEM_ARVALID & MEM_ARREADY), .CLK(CLK), .RSTn(RSTn));
wire [31:0] aw_wrap_size;
wire [31:0] ar_wrap_size;
wire aw_wrap_en, ar_wrap_en;
wire axi_awready_set, axi_awready_rst, axi_awready_qout;
wire axi_awv_awr_flag_set, axi_awv_awr_flag_rst, axi_awv_awr_flag_qout;
wire [31:0] axi_awaddr_dnxta;
wire [31:0] axi_awaddr_dnxtb;
wire [31:0] axi_awaddr_qout;
wire axi_awaddr_ena, axi_awaddr_enb;
wire axi_awburst_en;
wire [1:0] axi_awburst_dnxt;
wire [1:0] axi_awburst_qout;
wire axi_awlen_en;
wire [7:0] axi_awlen_dnxt;
wire [7:0] axi_awlen_qout;
wire [7:0] axi_awlen_cnt_dnxta;
wire [7:0] axi_awlen_cnt_dnxtb;
wire [7:0] axi_awlen_cnt_qout;
wire axi_awlen_cnt_ena, axi_awlen_cnt_enb;
wire axi_wready_set, axi_wready_rst, axi_wready_qout;
wire axi_bvalid_set, axi_bvalid_rst, axi_bvalid_qout;
wire axi_arready_set, axi_arready_rst, axi_arready_qout;
wire axi_arv_arr_flag_set, axi_arv_arr_flag_rst, axi_arv_arr_flag_qout;
wire [31:0] axi_araddr_dnxta;
wire [31:0] axi_araddr_dnxtb;
wire [31:0] axi_araddr_qout;
wire axi_araddr_ena, axi_araddr_enb, axi_arburst_en;
wire [1:0] axi_arburst_dnxt;
wire [1:0] axi_arburst_qout;
wire axi_arlen_en;
wire [7:0] axi_arlen_dnxt;
wire [7:0] axi_arlen_qout;
wire [7:0] axi_arlen_cnt_dnxta;
wire [7:0] axi_arlen_cnt_dnxtb;
wire [7:0] axi_arlen_cnt_qout;
wire axi_arlen_cnt_ena, axi_arlen_cnt_enb;
wire axi_rvalid_set, axi_rvalid_rst, axi_rvalid_qout;
wire axi_rlast_set, axi_rlast_rst, axi_rlast_qout;
assign MEM_AWREADY = axi_awready_qout;
assign MEM_WREADY = axi_wready_qout;
assign MEM_BRESP = 2'b00;
assign MEM_BVALID = axi_bvalid_qout;
assign MEM_ARREADY = axi_arready_qout;
assign MEM_RRESP = 2'b00;
assign MEM_RLAST = axi_rlast_qout;
assign MEM_RVALID = axi_rvalid_qout;
assign axi_awready_set = (~axi_awready_qout & MEM_AWVALID & ~axi_awv_awr_flag_qout & ~axi_arv_arr_flag_qout);
assign axi_awready_rst = ~(~axi_awready_qout & MEM_AWVALID & ~axi_awv_awr_flag_qout & ~axi_arv_arr_flag_qout) & ~(MEM_WLAST & axi_wready_qout);
gen_rsffr axi_awready_rsffr (.set_in(axi_awready_set), .rst_in(axi_awready_rst), .qout(axi_awready_qout), .CLK(CLK), .RSTn(RSTn));
assign axi_awv_awr_flag_set = (~axi_awready_qout & MEM_AWVALID & ~axi_awv_awr_flag_qout & ~axi_arv_arr_flag_qout);
assign axi_awv_awr_flag_rst = ( axi_awready_qout | ~MEM_AWVALID | axi_awv_awr_flag_qout | axi_arv_arr_flag_qout) & (MEM_WLAST & axi_wready_qout);
gen_rsffr axi_awv_awr_flag_rsffr (.set_in(axi_awv_awr_flag_set), .rst_in(axi_awv_awr_flag_rst), .qout(axi_awv_awr_flag_qout), .CLK(CLK), .RSTn(RSTn));
assign axi_awaddr_dnxta = MEM_AWADDR;
assign axi_awaddr_dnxtb = ( {32{axi_awburst_qout == 2'b00}} & axi_awaddr_qout )
|
( {32{axi_awburst_qout == 2'b01}} & axi_awaddr_qout + (1<<ADDR_LSB) );
assign axi_awaddr_ena = ~axi_awready_qout & MEM_AWVALID & ~axi_awv_awr_flag_qout;
assign axi_awaddr_enb = (axi_awlen_cnt_qout <= axi_awlen_qout) & axi_wready_qout & MEM_WVALID;
gen_dpdffren # (.DW(32)) axi_awaddr_dpdffren( .dnxta(axi_awaddr_dnxta), .ena(axi_awaddr_ena), .dnxtb(axi_awaddr_dnxtb), .enb(axi_awaddr_enb), .qout(axi_awaddr_qout), .CLK(CLK), .RSTn(RSTn) );
assign axi_awburst_en = (~axi_awready_qout & MEM_AWVALID & ~axi_awv_awr_flag_qout);
assign axi_awburst_dnxt = MEM_AWBURST;
gen_dffren # (.DW(2)) axi_awburst_dffren (.dnxt(axi_awburst_dnxt), .qout(axi_awburst_qout), .en(axi_awburst_en), .CLK(CLK), .RSTn(RSTn));
assign axi_awlen_en = ~axi_awready_qout & MEM_AWVALID & ~axi_awv_awr_flag_qout;
assign axi_awlen_dnxt = MEM_AWLEN;
gen_dffren # (.DW(8)) axi_awlen_dffren (.dnxt(axi_awlen_dnxt), .qout(axi_awlen_qout), .en(axi_awlen_en), .CLK(CLK), .RSTn(RSTn));
assign axi_awlen_cnt_dnxta = 8'd0;
assign axi_awlen_cnt_dnxtb = axi_awlen_cnt_qout + 8'd1;
assign axi_awlen_cnt_ena = ~axi_awready_qout & MEM_AWVALID & ~axi_awv_awr_flag_qout;
assign axi_awlen_cnt_enb = (axi_awlen_cnt_qout <= axi_awlen_qout) & axi_wready_qout & MEM_WVALID;
gen_dpdffren # (.DW(8)) axi_awlen_cnt_dpdffren( .dnxta(axi_awlen_cnt_dnxta), .ena(axi_awlen_cnt_ena), .dnxtb(axi_awlen_cnt_dnxtb), .enb(axi_awlen_cnt_enb), .qout(axi_awlen_cnt_qout), .CLK(CLK), .RSTn(RSTn) );
assign axi_wready_set = ~axi_wready_qout & MEM_WVALID & axi_awv_awr_flag_qout;
assign axi_wready_rst = axi_wready_qout & MEM_WLAST;
gen_rsffr axi_wready_rsffr (.set_in(axi_wready_set), .rst_in(axi_wready_rst), .qout(axi_wready_qout), .CLK(CLK), .RSTn(RSTn));
assign axi_bvalid_set = ~axi_bvalid_qout & axi_awv_awr_flag_qout & axi_wready_qout & MEM_WVALID & MEM_WLAST;
assign axi_bvalid_rst = axi_bvalid_qout & MEM_BREADY;
gen_rsffr axi_bvalid_rsffr (.set_in(axi_bvalid_set), .rst_in(axi_bvalid_rst), .qout(axi_bvalid_qout), .CLK(CLK), .RSTn(RSTn));
assign axi_arready_set = (~axi_arready_qout & MEM_ARVALID & ~axi_awv_awr_flag_qout & ~axi_arv_arr_flag_qout);
assign axi_arready_rst = ~(~axi_arready_qout & MEM_ARVALID & ~axi_awv_awr_flag_qout & ~axi_arv_arr_flag_qout) & ~(axi_rvalid_qout & MEM_RREADY & axi_arlen_cnt_qout == axi_arlen_qout);
gen_rsffr axi_arready_rsffr (.set_in(axi_arready_set), .rst_in(axi_arready_rst), .qout(axi_arready_qout), .CLK(CLK), .RSTn(RSTn));
assign axi_arv_arr_flag_set = (~axi_arready_qout & MEM_ARVALID & ~axi_awv_awr_flag_qout & ~axi_arv_arr_flag_qout);
assign axi_arv_arr_flag_rst = ( axi_arready_qout | ~MEM_ARVALID | axi_awv_awr_flag_qout | axi_arv_arr_flag_qout) & (axi_rvalid_qout & MEM_RREADY & axi_arlen_cnt_qout == axi_arlen_qout);
gen_rsffr axi_arv_arr_flag_rsffr (.set_in(axi_arv_arr_flag_set), .rst_in(axi_arv_arr_flag_rst), .qout(axi_arv_arr_flag_qout), .CLK(CLK), .RSTn(RSTn));
assign axi_araddr_dnxta = MEM_ARADDR;
assign axi_araddr_dnxtb = ({32{axi_arburst_qout == 2'b00}} & axi_araddr_qout)
|
({32{axi_arburst_qout == 2'b01}} & axi_araddr_qout + (1<<ADDR_LSB));
assign axi_araddr_ena = (~axi_arready_qout & MEM_ARVALID & ~axi_arv_arr_flag_qout);
assign axi_araddr_enb = ((axi_arlen_cnt_qout <= axi_arlen_qout) & axi_rvalid_qout & MEM_RREADY);
gen_dpdffren # (.DW(32)) axi_araddr_dpdffren( .dnxta(axi_araddr_dnxta), .ena(axi_araddr_ena), .dnxtb(axi_araddr_dnxtb), .enb(axi_araddr_enb), .qout(axi_araddr_qout), .CLK(CLK), .RSTn(RSTn) );
assign axi_arburst_en = (~axi_arready_qout & MEM_ARVALID & ~axi_arv_arr_flag_qout);
assign axi_arburst_dnxt = MEM_ARBURST;
gen_dffren # (.DW(2)) axi_arburst_dffren (.dnxt(axi_arburst_dnxt), .qout(axi_arburst_qout), .en(axi_arburst_en), .CLK(CLK), .RSTn(RSTn));
assign axi_arlen_en = (~axi_arready_qout && MEM_ARVALID && ~axi_arv_arr_flag_qout);
assign axi_arlen_dnxt = MEM_ARLEN;
gen_dffren # (.DW(8)) axi_arlen_dffren (.dnxt(axi_arlen_dnxt), .qout(axi_arlen_qout), .en(axi_arlen_en), .CLK(CLK), .RSTn(RSTn));
assign axi_rlast_set = ((axi_arlen_cnt_qout == axi_arlen_qout) & ~axi_rlast_qout & axi_arv_arr_flag_qout ) ;
assign axi_rlast_rst = (~axi_arready_qout & MEM_ARVALID & ~axi_arv_arr_flag_qout) | (((axi_arlen_cnt_qout <= axi_arlen_qout) | axi_rlast_qout | ~axi_arv_arr_flag_qout ) & ( axi_rvalid_qout & MEM_RREADY));
gen_rsffr axi_rlast_rsffr (.set_in(axi_rlast_set), .rst_in(axi_rlast_rst), .qout(axi_rlast_qout), .CLK(CLK), .RSTn(RSTn));
assign axi_arlen_cnt_dnxta = 8'd0;
assign axi_arlen_cnt_dnxtb = axi_arlen_cnt_qout + 8'd1;
assign axi_arlen_cnt_ena = (~axi_arready_qout & MEM_ARVALID & ~axi_arv_arr_flag_qout);
assign axi_arlen_cnt_enb = ((axi_arlen_cnt_qout <= axi_arlen_qout) & axi_rvalid_qout & MEM_RREADY);
gen_dpdffren # (.DW(8)) axi_arlen_cnt_dpdffren( .dnxta(axi_arlen_cnt_dnxta), .ena(axi_arlen_cnt_ena), .dnxtb(axi_arlen_cnt_dnxtb), .enb(axi_arlen_cnt_enb), .qout(axi_arlen_cnt_qout), .CLK(CLK), .RSTn(RSTn) );
assign axi_rvalid_set = ~axi_rvalid_qout & axi_arv_arr_flag_qout;
assign axi_rvalid_rst = axi_rvalid_qout & MEM_RREADY;
gen_rsffr axi_rvalid_rsffr (.set_in(axi_rvalid_set), .rst_in(axi_rvalid_rst), .qout(axi_rvalid_qout), .CLK(CLK), .RSTn(RSTn));
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------
wire [DW-1:0] data_w = MEM_WDATA;
wire [AW-1:0] addr_w = axi_awaddr_qout[ADDR_LSB +: AW];
wire [DW/8-1:0] data_wstrb = MEM_WSTRB;
wire en_w = axi_awv_awr_flag_qout;
wire [DW-1:0] data_r;
assign MEM_RDATA = data_r;
wire [AW-1:0] addr_r = axi_araddr_qout[ADDR_LSB +: AW];
wire en_r = axi_arv_arr_flag_qout;
gen_sram # ( .DW(DW), .AW(AW) ) i_sram
(
.data_w(data_w),
.addr_w(addr_w),
.data_wstrb(data_wstrb),
.en_w(en_w),
.data_r(data_r),
.addr_r(addr_r),
.en_r(en_r),
.CLK(CLK)
);
endmodule

209
tb/vtb/debuger.v Normal file
View File

@@ -0,0 +1,209 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module debuger (
output success,
input [3:0] DEBUGER_AWID,
output [3:0] DEBUGER_BID,
input [3:0] DEBUGER_ARID,
output [3:0] DEBUGER_RID,
input [31:0] DEBUGER_AWADDR,
input DEBUGER_AWVALID,
output DEBUGER_AWREADY,
input [31:0] DEBUGER_WDATA,
input [3:0] DEBUGER_WSTRB,
input DEBUGER_WVALID,
output DEBUGER_WREADY,
output [1:0] DEBUGER_BRESP,
output DEBUGER_BVALID,
input DEBUGER_BREADY,
input [31:0] DEBUGER_ARADDR,
input DEBUGER_ARVALID,
output DEBUGER_ARREADY,
output [31:0] DEBUGER_RDATA,
output [1:0] DEBUGER_RRESP,
output DEBUGER_RVALID,
input DEBUGER_RREADY,
input CLK,
input RSTn
);
gen_dffren # (.DW(4)) awid_dffren (.dnxt(DEBUGER_AWID), .qout(DEBUGER_BID), .en(DEBUGER_AWVALID & DEBUGER_AWREADY), .CLK(CLK), .RSTn(RSTn));
gen_dffren # (.DW(4)) arid_dffren (.dnxt(DEBUGER_ARID), .qout(DEBUGER_RID), .en(DEBUGER_ARVALID & DEBUGER_ARREADY), .CLK(CLK), .RSTn(RSTn));
assign DEBUGER_AWREADY = debuger_awready_qout;
assign DEBUGER_WREADY = debuger_wready_qout;
assign DEBUGER_BRESP = 2'b0;
assign DEBUGER_BVALID = debuger_bvalid_qout;
assign DEBUGER_ARREADY = debuger_arready_qout;
assign DEBUGER_RDATA = 32'b0;
assign DEBUGER_RRESP = 2'b0;
assign DEBUGER_RVALID = debuger_rvalid_qout;
wire debuger_awready_set, debuger_awready_rst, debuger_awready_qout;
wire aw_en_set, aw_en_rst, aw_en_qout;
wire debuger_wready_set, debuger_wready_rst, debuger_wready_qout;
assign debuger_awready_set = ~debuger_awready_qout & DEBUGER_AWVALID & DEBUGER_WVALID;
assign debuger_awready_rst = ~debuger_awready_set & (DEBUGER_BREADY & debuger_bvalid_qout);
assign debuger_wready_set = ~debuger_wready_qout & DEBUGER_WVALID & DEBUGER_AWVALID;
assign debuger_wready_rst = ~debuger_wready_set;
gen_rsffr #(.DW(1)) debuger_awready_rsffr (.set_in(debuger_awready_set), .rst_in(debuger_awready_rst), .qout(debuger_awready_qout), .CLK(CLK), .RSTn(RSTn));
gen_rsffr #(.DW(1)) debuger_wready_rsffr (.set_in(debuger_wready_set), .rst_in(debuger_wready_rst), .qout(debuger_wready_qout), .CLK(CLK), .RSTn(RSTn));
wire debuger_bvalid_set, debuger_bvalid_rst, debuger_bvalid_qout;
wire debuger_arready_set, debuger_arready_rst, debuger_arready_qout;
wire debuger_rvalid_set, debuger_rvalid_rst, debuger_rvalid_qout;
assign debuger_bvalid_set = debuger_awready_qout && DEBUGER_AWVALID && ~debuger_bvalid_qout && debuger_wready_qout && DEBUGER_WVALID;
assign debuger_bvalid_rst = ~debuger_bvalid_set & (DEBUGER_BREADY && debuger_bvalid_qout);
assign debuger_arready_set = (~debuger_arready_qout && DEBUGER_ARVALID);
assign debuger_arready_rst = ~debuger_arready_set;
assign debuger_rvalid_set = (debuger_arready_qout & DEBUGER_ARVALID & ~debuger_rvalid_qout);
assign debuger_rvalid_rst = ~debuger_rvalid_set & (debuger_rvalid_qout & DEBUGER_RREADY);
gen_rsffr #(.DW(1)) debuger_bvalid_rsffr (.set_in(debuger_bvalid_set), .rst_in(debuger_bvalid_rst), .qout(debuger_bvalid_qout), .CLK(CLK), .RSTn(RSTn));
gen_rsffr #(.DW(1)) debuger_arready_rsffr (.set_in(debuger_arready_set), .rst_in(debuger_arready_rst), .qout(debuger_arready_qout), .CLK(CLK), .RSTn(RSTn));
gen_rsffr #(.DW(1)) debuger_rvalid_rsffr (.set_in(debuger_rvalid_set), .rst_in(debuger_rvalid_rst), .qout(debuger_rvalid_qout), .CLK(CLK), .RSTn(RSTn));
`define UART_TX 32'h60000000
`define TIMER 32'h60000008
`define COTRL 32'h60000010
`define COTRL_COREMARK 32'h60000020
reg [63:0] cycle_cnt;
reg timer_start;
reg success_reg = 1'b0;
assign success = success_reg;
always @(posedge CLK or negedge RSTn) begin
if (~RSTn) begin
cycle_cnt <= 0;
timer_start <= 1'b0;
end
else begin
if ( (DEBUGER_AWADDR == `TIMER) & DEBUGER_AWVALID & DEBUGER_AWREADY & DEBUGER_WVALID & DEBUGER_WREADY & (DEBUGER_WDATA == 32'd1)) begin
timer_start <= 1'b1;
end
if ( (DEBUGER_AWADDR == `TIMER) & DEBUGER_AWVALID & DEBUGER_WVALID & (DEBUGER_WDATA == 32'd0)) begin
timer_start <= 1'b0;
end
if (timer_start) begin
cycle_cnt <= cycle_cnt + 1;
end
else begin
cycle_cnt <= cycle_cnt;
end
end
end
always @(posedge CLK) begin
if ( (DEBUGER_AWADDR == `UART_TX) & DEBUGER_AWVALID & DEBUGER_AWREADY & DEBUGER_WVALID & DEBUGER_WREADY) begin
$write("%c", DEBUGER_WDATA[7:0]);
end
end
integer file;
always @(posedge CLK ) begin
if ( (DEBUGER_AWADDR == `COTRL) & DEBUGER_AWVALID & DEBUGER_AWREADY & DEBUGER_WVALID & DEBUGER_WREADY & (DEBUGER_WDATA == 32'd1)) begin
$display("cycle_cnt = %d", cycle_cnt);
$display( "The DMIPS/MHz is %f", 1000000.0/(cycle_cnt/500.0)/1757.0 );
file = $fopen("./dhrystone.json", "w");
$fwrite(file, "{\n \"schemaVersion\": 1, \n \"label\": \"\", \n \"message\": \"%f\", \n \"color\": \"ff69b4\" \n}", 1000000.0/(cycle_cnt/500.0)/1757.0 );
$fclose(file);
success_reg <= 1'b1;
end
if ( (DEBUGER_AWADDR == `COTRL_COREMARK) & DEBUGER_AWVALID & DEBUGER_AWREADY & DEBUGER_WVALID & DEBUGER_WREADY & (DEBUGER_WDATA == 32'd1)) begin
$display("Total ticks : %d", cycle_cnt);
$display("CoreMark 1.0 : %f",1*1*1000000.0/cycle_cnt);
file = $fopen("./coremark.json", "w");
$fwrite(file, "{\n \"schemaVersion\": 1, \n \"label\": \"\", \n \"message\": \"%f\", \n \"color\": \"368fb4\" \n}", 1*1*1000000.0/cycle_cnt );
$fclose(file);
success_reg <= 1'b1;
end
end
endmodule

1426
tb/vtb/eth_phy.v Normal file
View File

File diff suppressed because it is too large Load Diff

90
tb/vtb/eth_phy_defines.v Normal file
View File

@@ -0,0 +1,90 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// File name: eth_phy_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Tadej Markovic, tadej@opencores.org ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/09/13 11:57:20 mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
//
//
// Address of PHY device (LXT971A)
`define ETH_PHY_ADDR 5'h01
// LED/Configuration pins on PHY device - see the specification, page 26, table 8
// Initial set of bits 13, 12 and 8 of Control Register
`define LED_CFG1 1'b0
`define LED_CFG2 1'b0
`define LED_CFG3 1'b1
// Supported speeds and physical ports - see the specification, page 67, table 41
// Set bits 15 to 9 of Status Register
`define SUPPORTED_SPEED_AND_PORT 7'h3F
// Extended status register (address 15)
// Set bit 8 of Status Register
`define EXTENDED_STATUS 1'b0
// Default status bits - see the specification, page 67, table 41
// Set bits 6 to 0 of Status Register
`define DEFAULT_STATUS 7'h09
// PHY ID 1 number - see the specification, page 68, table 42
// Set bits of Phy Id Register 1
`define PHY_ID1 16'h0013
// PHY ID 2 number - see the specification, page 68, table 43
// Set bits 15 to 10 of Phy Id Register 2
`define PHY_ID2 6'h1E
// Manufacturer MODEL number - see the specification, page 68, table 43
// Set bits 9 to 4 of Phy Id Register 2
`define MAN_MODEL_NUM 6'h0E
// Manufacturer REVISION number - see the specification, page 68, table 43
// Set bits 3 to 0 of Phy Id Register 2
`define MAN_REVISION_NUM 4'h2

57
tb/vtb/gen_dffr.v Normal file
View File

@@ -0,0 +1,57 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module gen_dffr # (
parameter DW = 32,
parameter rstValue = {DW{1'b0}}
)
(
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input CLK,
input RSTn
);
reg [DW-1:0] qout_r;
always @(posedge CLK or negedge RSTn) begin
if ( ~RSTn )
qout_r <= #1 rstValue;
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule

62
tb/vtb/gen_dffren.v Normal file
View File

@@ -0,0 +1,62 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module gen_dffren # (
parameter DW = 32,
parameter rstValue = {DW{1'b0}}
)
(
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input en,
input CLK,
input RSTn
);
wire [DW-1:0] dffren_dnxt;
wire [DW-1:0] dffren_qout;
gen_dffr # ( .DW(DW), .rstValue(rstValue) ) dffren
(
.dnxt(dffren_dnxt),
.qout(dffren_qout),
.CLK(CLK),
.RSTn(RSTn)
);
assign dffren_dnxt = en ? dnxt : dffren_qout;
assign qout = dffren_qout;
endmodule

69
tb/vtb/gen_dpdffren.v Normal file
View File

@@ -0,0 +1,69 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module gen_dpdffren #(
parameter DW = 32,
parameter rstValue = {DW{1'b0}}
)
(
input [DW-1:0] dnxta,
input ena,
input [DW-1:0] dnxtb,
input enb,
output [DW-1:0] qout,
input CLK,
input RSTn
);
wire en;
wire [DW-1:0] dnxt;
assign en = ena | enb;
assign dnxt = {DW{ena}} & dnxta
|
{DW{(~ena)&enb}} & dnxtb;
gen_dffren # ( .DW(DW), .rstValue(rstValue) ) dffren
(
.dnxt(dnxt),
.qout(qout),
.en(en),
.CLK(CLK),
.RSTn(RSTn)
);
endmodule

70
tb/vtb/gen_rsffr.v Normal file
View File

@@ -0,0 +1,70 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module gen_rsffr # (
parameter DW = 1,
parameter rstValue = {DW{1'b0}}
)
(
input [DW-1:0] set_in,
input [DW-1:0] rst_in,
output [DW-1:0] qout,
input CLK,
input RSTn
);
reg [DW-1:0] qout_r;
generate
for ( genvar i = 0; i < DW; i = i + 1 ) begin
always @(posedge CLK or negedge RSTn) begin
if ( ~RSTn ) begin
qout_r[i] <= #1 rstValue[i];
end
else begin
qout_r[i] <= #1 qout_r[i];
if ( set_in[i] ) begin
qout_r[i] <= #1 1'b1;
end
if ( rst_in[i] ) begin
qout_r[i] <= #1 1'b0;
end
end
end
end
endgenerate
assign qout = qout_r;
endmodule

54
tb/vtb/gen_slffr.v Normal file
View File

@@ -0,0 +1,54 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module gen_slffr # (
parameter DW = 1,
parameter rstValue = 1'b0
)
(
input [DW-1:0] set_in,
input [DW-1:0] rst_in,
output [DW-1:0] qout,
input CLK,
input RSTn
);
wire [DW-1:0] rsffr_qout;
gen_rsffr # ( .DW(DW), .rstValue(rstValue)) rsffr ( .set_in(set_in), .rst_in(rst_in), .qout(rsffr_qout), .CLK(CLK), .RSTn(RSTn));
assign qout = set_in | rsffr_qout;
//ASSERT
always @( posedge CLK ) begin
if ( set_in & rst_in ) begin
$display("Assert Fail at gen_slff");
$finish;
end
end
endmodule

97
tb/vtb/gen_sram.v Normal file
View File

@@ -0,0 +1,97 @@
/*
Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`timescale 1 ns / 1 ps
module gen_sram #
(
parameter DW = 32,
parameter AW = 14
)
(
input [DW-1:0] data_w,
input [AW-1:0] addr_w,
input [(DW+7)/8-1:0] data_wstrb,
input en_w,
output [DW-1:0] data_r,
input [AW-1:0] addr_r,
input en_r,
input CLK
);
localparam DP = 2**AW;
localparam DW_ZM = (DW+7)/8*8;
reg [DW_ZM-1:0] ram[0:DP-1];
reg [DW_ZM-1:0] data_r_reg;
wire [DW_ZM-1:0] data_w_zmask = {DW_ZM{1'b0}} | data_w;
generate
for ( genvar i = 0; i < (DW+7)/8; i = i + 1) begin
always @(posedge CLK) begin
if (en_w) begin
if (data_wstrb[i]) begin
ram[addr_w][i*8+:8] <= #1 data_w_zmask[i*8+:8] ;
end
end
if (en_r) begin
data_r_reg[i*8+:8] <= #1 ram[addr_r][i*8+:8];
end
end
end
endgenerate
assign data_r = data_r_reg[DW-1:0];
// integer i;
// initial begin
// for ( i = 0; i < DP; i = i + 1 ) begin
// ram[i] = {((DW+31)/32){$random}};
// end
// data_r_reg = {((DW+31)/32){$random}};
// end
endmodule

212
tb/vtb/tb_eth_defines.v Normal file
View File

@@ -0,0 +1,212 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// tb_eth_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/11/19 20:27:46 mohor
// Temp version.
//
// Revision 1.9 2002/10/09 13:16:51 tadejm
// Just back-up; not completed testbench and some testcases are not
// wotking properly yet.
//
// Revision 1.8 2002/09/13 18:41:45 mohor
// Rearanged testcases
//
// Revision 1.7 2002/09/13 12:29:14 mohor
// Headers changed.
//
// Revision 1.6 2002/09/13 11:57:20 mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
// Revision 1.3 2002/07/19 13:57:53 mohor
// Testing environment also includes traffic cop, memory interface and host
// interface.
//
// Revision 1.2 2002/05/03 10:22:17 mohor
// TX_BUF_BASE changed.
//
// Revision 1.1 2002/03/19 12:53:54 mohor
// Some defines that are used in testbench only were moved to tb_eth_defines.v
// file.
//
//
//
//
//`define VERBOSE // if log files of device modules are written
`define MULTICAST_XFR 0
`define UNICAST_XFR 1
`define BROADCAST_XFR 2
`define UNICAST_WRONG_XFR 3
`define ETH_BASE 32'hd0000000
`define ETH_WIDTH 32'h800
`define MEMORY_BASE 32'h2000
`define MEMORY_WIDTH 32'h10000
`define TX_BUF_BASE `MEMORY_BASE
`define RX_BUF_BASE `MEMORY_BASE + 32'h8000
`define TX_BD_BASE `ETH_BASE + 32'h00000400
`define RX_BD_BASE `ETH_BASE + 32'h00000600
/* Tx BD */
`define ETH_TX_BD_READY 32'h8000 /* Tx BD Ready */
`define ETH_TX_BD_IRQ 32'h4000 /* Tx BD IRQ Enable */
`define ETH_TX_BD_WRAP 32'h2000 /* Tx BD Wrap (last BD) */
`define ETH_TX_BD_PAD 32'h1000 /* Tx BD Pad Enable */
`define ETH_TX_BD_CRC 32'h0800 /* Tx BD CRC Enable */
`define ETH_TX_BD_UNDERRUN 32'h0100 /* Tx BD Underrun Status */
`define ETH_TX_BD_RETRY 32'h00F0 /* Tx BD Retry Status */
`define ETH_TX_BD_RETLIM 32'h0008 /* Tx BD Retransmission Limit Status */
`define ETH_TX_BD_LATECOL 32'h0004 /* Tx BD Late Collision Status */
`define ETH_TX_BD_DEFER 32'h0002 /* Tx BD Defer Status */
`define ETH_TX_BD_CARRIER 32'h0001 /* Tx BD Carrier Sense Lost Status */
/* Rx BD */
`define ETH_RX_BD_EMPTY 32'h8000 /* Rx BD Empty */
`define ETH_RX_BD_IRQ 32'h4000 /* Rx BD IRQ Enable */
`define ETH_RX_BD_WRAP 32'h2000 /* Rx BD Wrap (last BD) */
`define ETH_RX_BD_MISS 32'h0080 /* Rx BD Miss Status */
`define ETH_RX_BD_OVERRUN 32'h0040 /* Rx BD Overrun Status */
`define ETH_RX_BD_INVSIMB 32'h0020 /* Rx BD Invalid Symbol Status */
`define ETH_RX_BD_DRIBBLE 32'h0010 /* Rx BD Dribble Nibble Status */
`define ETH_RX_BD_TOOLONG 32'h0008 /* Rx BD Too Long Status */
`define ETH_RX_BD_SHORT 32'h0004 /* Rx BD Too Short Frame Status */
`define ETH_RX_BD_CRCERR 32'h0002 /* Rx BD CRC Error Status */
`define ETH_RX_BD_LATECOL 32'h0001 /* Rx BD Late Collision Status */
/* Register space */
`define ETH_MODER `ETH_BASE + 32'h00 /* Mode Register */
`define ETH_INT `ETH_BASE + 32'h04 /* Interrupt Source Register */
`define ETH_INT_MASK `ETH_BASE + 32'h08 /* Interrupt Mask Register */
`define ETH_IPGT `ETH_BASE + 32'h0C /* Back to Bak Inter Packet Gap Register */
`define ETH_IPGR1 `ETH_BASE + 32'h10 /* Non Back to Back Inter Packet Gap Register 1 */
`define ETH_IPGR2 `ETH_BASE + 32'h14 /* Non Back to Back Inter Packet Gap Register 2 */
`define ETH_PACKETLEN `ETH_BASE + 32'h18 /* Packet Length Register (min. and max.) */
`define ETH_COLLCONF `ETH_BASE + 32'h1C /* Collision and Retry Configuration Register */
`define ETH_TX_BD_NUM `ETH_BASE + 32'h20 /* Transmit Buffer Descriptor Number Register */
`define ETH_CTRLMODER `ETH_BASE + 32'h24 /* Control Module Mode Register */
`define ETH_MIIMODER `ETH_BASE + 32'h28 /* MII Mode Register */
`define ETH_MIICOMMAND `ETH_BASE + 32'h2C /* MII Command Register */
`define ETH_MIIADDRESS `ETH_BASE + 32'h30 /* MII Address Register */
`define ETH_MIITX_DATA `ETH_BASE + 32'h34 /* MII Transmit Data Register */
`define ETH_MIIRX_DATA `ETH_BASE + 32'h38 /* MII Receive Data Register */
`define ETH_MIISTATUS `ETH_BASE + 32'h3C /* MII Status Register */
`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
`define ETH_TX_CTRL `ETH_BASE + 32'h50 /* Tx Control Register */
/* MODER Register */
`define ETH_MODER_RXEN 32'h00000001 /* Receive Enable */
`define ETH_MODER_TXEN 32'h00000002 /* Transmit Enable */
`define ETH_MODER_NOPRE 32'h00000004 /* No Preamble */
`define ETH_MODER_BRO 32'h00000008 /* Reject Broadcast */
`define ETH_MODER_IAM 32'h00000010 /* Use Individual Hash */
`define ETH_MODER_PRO 32'h00000020 /* Promiscuous (receive all) */
`define ETH_MODER_IFG 32'h00000040 /* Min. IFG not required */
`define ETH_MODER_LOOPBCK 32'h00000080 /* Loop Back */
`define ETH_MODER_NOBCKOF 32'h00000100 /* No Backoff */
`define ETH_MODER_EXDFREN 32'h00000200 /* Excess Defer */
`define ETH_MODER_FULLD 32'h00000400 /* Full Duplex */
`define ETH_MODER_RST 32'h00000800 /* Reset MAC */
`define ETH_MODER_DLYCRCEN 32'h00001000 /* Delayed CRC Enable */
`define ETH_MODER_CRCEN 32'h00002000 /* CRC Enable */
`define ETH_MODER_HUGEN 32'h00004000 /* Huge Enable */
`define ETH_MODER_PAD 32'h00008000 /* Pad Enable */
`define ETH_MODER_RECSMALL 32'h00010000 /* Receive Small */
/* Interrupt Source Register */
`define ETH_INT_TXB 32'h00000001 /* Transmit Buffer IRQ */
`define ETH_INT_TXE 32'h00000002 /* Transmit Error IRQ */
`define ETH_INT_RXB 32'h00000004 /* Receive Buffer IRQ */
`define ETH_INT_RXE 32'h00000008 /* Receive Error IRQ */
`define ETH_INT_BUSY 32'h00000010 /* Busy IRQ */
`define ETH_INT_TXC 32'h00000020 /* Transmit Control Frame IRQ */
`define ETH_INT_RXC 32'h00000040 /* Received Control Frame IRQ */
/* Interrupt Mask Register */
`define ETH_INT_MASK_TXB 32'h00000001 /* Transmit Buffer IRQ Mask */
`define ETH_INT_MASK_TXE 32'h00000002 /* Transmit Error IRQ Mask */
`define ETH_INT_MASK_RXF 32'h00000004 /* Receive Frame IRQ Mask */
`define ETH_INT_MASK_RXE 32'h00000008 /* Receive Error IRQ Mask */
`define ETH_INT_MASK_BUSY 32'h00000010 /* Busy IRQ Mask */
`define ETH_INT_MASK_TXC 32'h00000020 /* Transmit Control Frame IRQ Mask */
`define ETH_INT_MASK_RXC 32'h00000040 /* Received Control Frame IRQ Mask */
/* Control Module Mode Register */
`define ETH_CTRLMODER_PASSALL 32'h00000001 /* Pass Control Frames */
`define ETH_CTRLMODER_RXFLOW 32'h00000002 /* Receive Control Flow Enable */
`define ETH_CTRLMODER_TXFLOW 32'h00000004 /* Transmit Control Flow Enable */
/* MII Mode Register */
`define ETH_MIIMODER_CLKDIV 32'h000000FF /* Clock Divider */
`define ETH_MIIMODER_NOPRE 32'h00000100 /* No Preamble */
`define ETH_MIIMODER_RST 32'h00000200 /* MIIM Reset */
/* MII Command Register */
`define ETH_MIICOMMAND_SCANSTAT 32'h00000001 /* Scan Status */
`define ETH_MIICOMMAND_RSTAT 32'h00000002 /* Read Status */
`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
/* MII Address Register */
`define ETH_MIIADDRESS_FIAD 32'h0000001F /* PHY Address */
`define ETH_MIIADDRESS_RGAD 32'h00001F00 /* RGAD Address */
/* MII Status Register */
`define ETH_MIISTATUS_LINKFAIL 0 /* Link Fail bit */
`define ETH_MIISTATUS_BUSY 1 /* MII Busy bit */
`define ETH_MIISTATUS_NVALID 2 /* Data in MII Status Register is invalid bit */
/* TX Control Register */
`define ETH_TX_CTRL_TXPAUSERQ 32'h10000 /* Send PAUSE request */
`define TIME $display(" Time: %0t", $time)