diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala
index 5218d55..1b1bc30 100644
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -20,7 +20,7 @@ class CDROutIO extends Bundle{
 
 class CDROut extends Module{
   val io: CDROutIO = IO(new CDROutIO)
-
+  def PRE_NUM = 2 //PRE_NUM should >= 2
 
 
   def STATE_IDLE  = 0.U
@@ -41,14 +41,14 @@ class CDROut extends Module{
 
   stateNext := Mux1H(Seq(
     (stateCurr === STATE_IDLE)     -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
-    (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
+    (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )),
     (stateCurr === STATE_PAYLOAD)  -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ),
   ))
 
   io.serDat := shiftData.extract(9)
   io.axis.ready :=
     bitCnt === 9.U & (
-      (stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
+      (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) |
       (stateCurr === STATE_PAYLOAD)
     )
 
@@ -67,8 +67,8 @@ class CDROut extends Module{
     } .otherwise{ //bitCnt === 9.U
       when( stateCurr === STATE_PREAMBLE ){
         shiftData := MuxCase( ETH_PRE, Array(
-          ( byteCnt === 6.U ) -> ETH_SFD,
-          ( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
+          ( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD,
+          ( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
         ))
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
         shiftData := Dualb4b5Encoder(io.axis.bits.tdata)