主机模拟FSMC模式不能背靠背传送，否则会出CRC以及CDR

src/main/scala/backBoard/BackBoardMst.scala

@@ -34,8 +34,8 @@ val reset_calib = Input(Bool())
   val crcErr         = Output(Bool())
   val linkErr        = Output(Bool())
 
-  // val testFail = Output(Bool())
+  val testFail = Output(Bool())
-  // val testDone = Output(Bool())
+  val testDone = Output(Bool())
 }
 
 // class Master_Status_Bundle extends Bundle{
@@ -93,8 +93,10 @@ class BackBoardMstBase extends Module{ //10M
 
 
   mirrorDown.io.clockr := io.oser_pclk.asBool
-  mirrorUp.io.clockw := io.oser_pclk.asBool
+  mirrorDown.io.clockw := io.ides_pclk.asBool //100M  
 
+  mirrorUp.io.clockw := io.oser_pclk.asBool
+  mirrorUp.io.clockr := io.ides_pclk.asBool   //100M
 
 
 
@@ -108,14 +110,15 @@ class BackBoardMstBase extends Module{ //10M
 
 
 trait BackBoardMstFSMC{ this: BackBoardMstBase =>
+  io.testDone := DontCare
+  io.testFail := DontCare
 
   val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
   val wrRegAddr        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }  //100M
   val wrRegData        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }  //100M
 
   withClockAndReset( io.ides_pclk.asClock, reset ){//100M
-    mirrorDown.io.clockw := io.ides_pclk.asBool //100M
+
-    mirrorUp.io.clockr := io.ides_pclk.asBool   //100M
 
     val fsmcCSSync  = ShiftRegisters( io.FSMC.cs,  3, false.B, true.B )
     val fsmcRDSync  = ShiftRegisters( io.FSMC.rd,  3, false.B, true.B )
@@ -222,34 +225,40 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 }
 
-// trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
+trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
-//   val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
+  io.FSMC.ADOut := DontCare
-//   when( powerUpCnt === 500.U ){
+  io.FSMC.ADOEn := DontCare
-//     ctrlInit := true.B
-//   }
 
-//   ctrlTransmit := statusInit
+  val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
+  when( powerUpCnt === 500.U ){
+    ctrlInit := true.B
+  }
+
+  val ( _, isTransmitTimeout ) = Counter(Range( 0,520), statusInit, false.B)
+  when(isTransmitTimeout){
+    ctrlTransmit := true.B
+  }
 
 
-//   mirrorDown.io.enw    := true.B
+  mirrorDown.io.enw    := true.B
-//   mirrorDown.io.addrw  := powerUpCnt
+  mirrorDown.io.addrw  := powerUpCnt
-//   mirrorDown.io.dataw  := "h5555".U
+  mirrorDown.io.dataw  := "h5555".U
 
   
-//   mirrorUp.io.enr    := false.B
+  mirrorUp.io.enr    := false.B
-//   mirrorUp.io.addrr  := 0.U
+  mirrorUp.io.addrr  := 0.U
 
-//   val testDone = RegInit(false.B)
+  val testDone = RegInit(false.B)
-//   val testFail = RegInit(false.B)
+  val testFail = RegInit(false.B)
-//   io.testDone := ~testDone
+  io.testDone := ~testDone
-//   io.testFail := ~testFail
+  io.testFail := ~testFail
-// }
+}
 
 
 
 abstract class BackBoardMstLVDSBase extends BackBoardMstBase 
-with BackBoardMstFSMC
+// with BackBoardMstFSMC
-// with BackBoardMstSim
+with BackBoardMstSim
 {
 
 

src/main/verilog/backBoardMstTop.v

@@ -3,6 +3,7 @@
 ////////////////////////
 
 module master_top(
+
   input resetn,
   input clock, 
     
@@ -124,13 +125,21 @@ CLKDIV Inst5_CLKDIVC(
 
 
 BackBoardMst i_BackBoardMst(
-    .io_FSMC_ADIn (io_FSMC_ADIn),
+    // .io_FSMC_ADIn (io_FSMC_ADIn),
-    .io_FSMC_ADOut(io_FSMC_ADOut),
+    // .io_FSMC_ADOut(io_FSMC_ADOut),
-    .io_FSMC_ADOEn(io_FSMC_ADOEn),
+    // .io_FSMC_ADOEn(io_FSMC_ADOEn),
-    .io_FSMC_cs(io_FSMC_cs),
+    // .io_FSMC_cs(io_FSMC_cs),
-    .io_FSMC_rd(io_FSMC_rd),
+    // .io_FSMC_rd(io_FSMC_rd),
-    .io_FSMC_wr(io_FSMC_wr),
+    // .io_FSMC_wr(io_FSMC_wr),
-    .io_FSMC_adv(io_FSMC_adv),
+    // .io_FSMC_adv(io_FSMC_adv),
+
+    .io_FSMC_ADIn ('d0),
+    .io_FSMC_ADOut(),
+    .io_FSMC_ADOEn(),
+    .io_FSMC_cs(1'b0),
+    .io_FSMC_rd(1'b0),
+    .io_FSMC_wr(1'b0),
+    .io_FSMC_adv(1'b0),
 
     .reset(~rst_n),
     .clock(clk_10m_a),