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主机模拟FSMC模式不能背靠背传送，否则会出CRC以及CDR

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RuigeLee
2024-02-22 16:34:01 +08:00
parent 411ad21db6
commit dba35faa6e
2 changed files with 48 additions and 30 deletions
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23
src/main/verilog/backBoardMstTop.v
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@@ -3,6 +3,7 @@
////////////////////////
module master_top(
input resetn,
input clock,
@@ -124,13 +125,21 @@ CLKDIV Inst5_CLKDIVC(
BackBoardMst i_BackBoardMst(
.io_FSMC_ADIn (io_FSMC_ADIn),
.io_FSMC_ADOut(io_FSMC_ADOut),
.io_FSMC_ADOEn(io_FSMC_ADOEn),
.io_FSMC_cs(io_FSMC_cs),
.io_FSMC_rd(io_FSMC_rd),
.io_FSMC_wr(io_FSMC_wr),
.io_FSMC_adv(io_FSMC_adv),
// .io_FSMC_ADIn (io_FSMC_ADIn),
// .io_FSMC_ADOut(io_FSMC_ADOut),
// .io_FSMC_ADOEn(io_FSMC_ADOEn),
// .io_FSMC_cs(io_FSMC_cs),
// .io_FSMC_rd(io_FSMC_rd),
// .io_FSMC_wr(io_FSMC_wr),
// .io_FSMC_adv(io_FSMC_adv),
.io_FSMC_ADIn ('d0),
.io_FSMC_ADOut(),
.io_FSMC_ADOEn(),
.io_FSMC_cs(1'b0),
.io_FSMC_rd(1'b0),
.io_FSMC_wr(1'b0),
.io_FSMC_adv(1'b0),
.reset(~rst_n),
.clock(clk_10m_a),