ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

主机模拟FSMC模式不能背靠背传送，否则会出CRC以及CDR

Browse Source
This commit is contained in:
RuigeLee
2024-02-22 16:34:01 +08:00
parent 411ad21db6
commit dba35faa6e
2 changed files with 48 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

55
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -34,8 +34,8 @@ val reset_calib = Input(Bool())
val crcErr = Output(Bool())
val linkErr = Output(Bool())
// val testFail = Output(Bool())
// val testDone = Output(Bool())
val testFail = Output(Bool())
val testDone = Output(Bool())
}
// class Master_Status_Bundle extends Bundle{
@@ -93,8 +93,10 @@ class BackBoardMstBase extends Module{ //10M
mirrorDown.io.clockr := io.oser_pclk.asBool
mirrorUp.io.clockw := io.oser_pclk.asBool
mirrorDown.io.clockw := io.ides_pclk.asBool //100M
mirrorUp.io.clockw := io.oser_pclk.asBool
mirrorUp.io.clockr := io.ides_pclk.asBool //100M
@@ -108,14 +110,15 @@ class BackBoardMstBase extends Module{ //10M
trait BackBoardMstFSMC{ this: BackBoardMstBase =>
io.testDone := DontCare
io.testFail := DontCare
val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
val wrRegAddr = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) } //100M
val wrRegData = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) } //100M
withClockAndReset( io.ides_pclk.asClock, reset ){//100M
mirrorDown.io.clockw := io.ides_pclk.asBool //100M
mirrorUp.io.clockr := io.ides_pclk.asBool //100M
val fsmcCSSync = ShiftRegisters( io.FSMC.cs, 3, false.B, true.B )
val fsmcRDSync = ShiftRegisters( io.FSMC.rd, 3, false.B, true.B )
@@ -222,34 +225,40 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
}
// trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
// val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
// when( powerUpCnt === 500.U ){
// ctrlInit := true.B
// }
trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
io.FSMC.ADOut := DontCare
io.FSMC.ADOEn := DontCare
// ctrlTransmit := statusInit
val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
when( powerUpCnt === 500.U ){
ctrlInit := true.B
}
val ( _, isTransmitTimeout ) = Counter(Range( 0,520), statusInit, false.B)
when(isTransmitTimeout){
ctrlTransmit := true.B
}
// mirrorDown.io.enw := true.B
// mirrorDown.io.addrw := powerUpCnt
// mirrorDown.io.dataw := "h5555".U
mirrorDown.io.enw := true.B
mirrorDown.io.addrw := powerUpCnt
mirrorDown.io.dataw := "h5555".U
// mirrorUp.io.enr := false.B
// mirrorUp.io.addrr := 0.U
mirrorUp.io.enr := false.B
mirrorUp.io.addrr := 0.U
// val testDone = RegInit(false.B)
// val testFail = RegInit(false.B)
// io.testDone := ~testDone
// io.testFail := ~testFail
// }
val testDone = RegInit(false.B)
val testFail = RegInit(false.B)
io.testDone := ~testDone
io.testFail := ~testFail
}
abstract class BackBoardMstLVDSBase extends BackBoardMstBase
with BackBoardMstFSMC
// with BackBoardMstSim
// with BackBoardMstFSMC
with BackBoardMstSim
{